On Mon, May 12, 2025 at 12:13:40AM +0300, Dmitry Baryshkov wrote:
> On Fri, May 09, 2025 at 02:28:55PM +0200, Konrad Dybcio wrote:
> > On 5/8/25 10:12 PM, Connor Abbott wrote:
> > > On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradyb...@kernel.org>
> > > wrote:
> > >>
> > >> From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
> > >>
> > >> Add a file that will serve as a single source of truth for UBWC
> > >> configuration data for various multimedia blocks.
> > >>
> > >> Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
> > >> ---
> >
> > [...]
> >
> > >> +struct qcom_ubwc_cfg_data {
> > >> + u32 ubwc_enc_version;
> > >> + /* Can be read from MDSS_BASE + 0x58 */
> > >> + u32 ubwc_dec_version;
> > >> + u32 ubwc_swizzle;
> > >> + int highest_bank_bit;
> > >> + bool ubwc_bank_spread;
> > >> + bool macrotile_mode;
> > >> + u32 mdss_reg_bus_bw;
> > >
> > > This doesn't really seem relevant to UBWC?
> >
> > I'll admit I just took it with the rest of properties for a simpler
> > transition.
> >
> > Generally, we could ma-a-a-aybe just make up a common value and pray it
> > doesn't
> > break anything, as we're taking numbers that translate to
> > ANYTHING_ABOVE_OFF or
> > ANYTHING_ABOVE_OFF_PLUS_1 in most cases wrt a cpu-ipblock path.
>
> I'd rather not do that. Let me check if I can cook it on top of your
> series.
See the attached patch.
--
With best wishes
Dmitry
>From cf3fe1a79c035dbf1b62143fe4219b15096bb8b1 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
Date: Mon, 12 May 2025 11:55:59 +0300
Subject: [PATCH] drm/msm: bring MDSS bandwidth data back to msm_mdss
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
---
drivers/gpu/drm/msm/msm_mdss.c | 85 +++++++++++++++++++++-------------
drivers/soc/qcom/ubwc_config.c | 20 --------
include/linux/soc/qcom/ubwc.h | 1 -
3 files changed, 54 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 71f5440994cc..a71597dc1e4d 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -24,7 +24,9 @@
#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
-#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
+struct msm_mdss_data {
+ u32 reg_bus_bw;
+};
struct msm_mdss {
struct device *dev;
@@ -38,6 +40,7 @@ struct msm_mdss {
struct irq_domain *domain;
} irq_controller;
const struct qcom_ubwc_cfg_data *mdss_data;
+ u32 reg_bus_bw;
struct icc_path *mdp_path[2];
u32 num_mdp_paths;
struct icc_path *reg_bus_path;
@@ -235,12 +238,8 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
for (i = 0; i < msm_mdss->num_mdp_paths; i++)
icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
- if (msm_mdss->mdss_data && msm_mdss->mdss_data->mdss_reg_bus_bw)
- icc_set_bw(msm_mdss->reg_bus_path, 0,
- msm_mdss->mdss_data->mdss_reg_bus_bw);
- else
- icc_set_bw(msm_mdss->reg_bus_path, 0,
- DEFAULT_REG_BW);
+ icc_set_bw(msm_mdss->reg_bus_path, 0,
+ msm_mdss->reg_bus_bw);
ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
if (ret) {
@@ -376,6 +375,7 @@ static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_d
static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
{
+ const struct msm_mdss_data *mdss_data;
struct msm_mdss *msm_mdss;
int ret;
int irq;
@@ -392,6 +392,12 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5
if (IS_ERR(msm_mdss->mdss_data))
return ERR_CAST(msm_mdss->mdss_data);
+ mdss_data = of_device_get_match_data(&pdev->dev);
+ if (!mdss_data)
+ return ERR_PTR(-EINVAL);
+
+ msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;
+
msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
if (IS_ERR(msm_mdss->mmio))
return ERR_CAST(msm_mdss->mmio);
@@ -509,31 +515,48 @@ static void mdss_remove(struct platform_device *pdev)
msm_mdss_destroy(mdss);
}
+static const struct msm_mdss_data data_57k = {
+ .reg_bus_bw = 57000,
+};
+
+static const struct msm_mdss_data data_74k = {
+ .reg_bus_bw = 74000,
+};
+
+static const struct msm_mdss_data data_76k8 = {
+ .reg_bus_bw = 76800,
+};
+
+static const struct msm_mdss_data data_153k6 = {
+ .reg_bus_bw = 153600,
+};
+
static const struct of_device_id mdss_dt_match[] = {
- { .compatible = "qcom,mdss" },
- { .compatible = "qcom,msm8998-mdss" },
- { .compatible = "qcom,qcm2290-mdss" },
- { .compatible = "qcom,sa8775p-mdss" },
- { .compatible = "qcom,sar2130p-mdss" },
- { .compatible = "qcom,sdm670-mdss" },
- { .compatible = "qcom,sdm845-mdss" },
- { .compatible = "qcom,sc7180-mdss" },
- { .compatible = "qcom,sc7280-mdss" },
- { .compatible = "qcom,sc8180x-mdss" },
- { .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm6115-mdss" },
- { .compatible = "qcom,sm6125-mdss" },
- { .compatible = "qcom,sm6150-mdss" },
- { .compatible = "qcom,sm6350-mdss" },
- { .compatible = "qcom,sm6375-mdss" },
- { .compatible = "qcom,sm7150-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
- { .compatible = "qcom,sm8350-mdss" },
- { .compatible = "qcom,sm8450-mdss" },
- { .compatible = "qcom,sm8550-mdss" },
- { .compatible = "qcom,sm8650-mdss" },
- { .compatible = "qcom,x1e80100-mdss"},
+ { .compatible = "qcom,mdss", .data = &data_153k6 },
+ { .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sa8775p-mdss", .data = &data_74k},
+ { .compatible = "qcom,sar2130p-mdss", .data = &data_74k},
+ { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sc7280-mdss", .data = &data_74k },
+ { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6115-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6125-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6150-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6350-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6375-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm7150-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm8150-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm8250-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm8350-mdss", .data = &data_74k },
+ { .compatible = "qcom,sm8450-mdss", .data = &data_74k },
+ { .compatible = "qcom,sm8550-mdss", .data = &data_57k },
+ { .compatible = "qcom,sm8650-mdss", .data = &data_57k },
+ /* TODO: x1e8: Add reg_bus_bw with real value */
+ { .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 3f81fb2aab28..43c9e6facb73 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -16,20 +16,17 @@ static const struct qcom_ubwc_cfg_data msm8937_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data msm8998_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data qcm2290_data = {
/* no UBWC */
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sa8775p_data = {
@@ -39,7 +36,6 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 0,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sar2130p_data = {
@@ -49,7 +45,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 0,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sc7180_data = {
@@ -58,7 +53,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data = {
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sc7280_data = {
@@ -68,7 +62,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sc8180x_data = {
@@ -76,7 +69,6 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = {
.ubwc_dec_version = UBWC_3_0,
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sc8280xp_data = {
@@ -86,21 +78,18 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sdm670_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sdm845_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm6115_data = {
@@ -109,7 +98,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data = {
.ubwc_swizzle = 7,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm6125_data = {
@@ -123,7 +111,6 @@ static const struct qcom_ubwc_cfg_data sm6150_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm6350_data = {
@@ -132,21 +119,18 @@ static const struct qcom_ubwc_cfg_data sm6350_data = {
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm7150_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm8150_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm8250_data = {
@@ -157,7 +141,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm8350_data = {
@@ -168,7 +151,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sm8550_data = {
@@ -179,7 +161,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 57000,
};
static const struct qcom_ubwc_cfg_data x1e80100_data = {
@@ -190,7 +171,6 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- /* TODO: Add mdss_reg_bus_bw with real value */
};
static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
index 450106e6aea0..e78645fc090f 100644
--- a/include/linux/soc/qcom/ubwc.h
+++ b/include/linux/soc/qcom/ubwc.h
@@ -17,7 +17,6 @@ struct qcom_ubwc_cfg_data {
int highest_bank_bit;
bool ubwc_bank_spread;
bool macrotile_mode;
- u32 mdss_reg_bus_bw;
};
#define UBWC_1_0 0x10000000
--
2.39.5
