Hi Prabhakar, Thank you for the patch.
On Mon, May 12, 2025 at 07:23:22PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> > > Simplify the high-speed clock frequency (HSFREQ) calculation by removing > the redundant multiplication and division by 8. The updated equation: > > hsfreq = (mode->clock * bpp) / (dsi->lanes); You can drop the parentheses around the second factor. You can actuall drop all prentheses. > > produces the same result while improving readability and clarity. > > Additionally, update the comment to clarify the relationship between HS > clock bit frequency, HS byte clock frequency, and HSFREQ. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> > Reviewed-by: Biju Das <biju.das...@bp.renesas.com> > --- > v4->v5: > - No changes > > v3->v4: > - No changes > > v2->v3: > - No changes > > v1->v2: > - Added Reviewed-by tag from Biju > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index ec8baecb9ba5..c5f698cd74f1 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -277,10 +277,10 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi > *dsi, > * hsclk: DSI HS Byte clock frequency (Hz) > * lanes: number of data lanes > * > - * hsclk(bit) = hsclk(byte) * 8 > + * hsclk(bit) = hsclk(byte) * 8 = hsfreq > */ > bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); > - hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); > + hsfreq = (mode->clock * bpp) / dsi->lanes; You can drop the parentheses here too. Reviewed-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com> > > ret = pm_runtime_resume_and_get(dsi->dev); > if (ret < 0) -- Regards, Laurent Pinchart
