Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:28PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
>
> Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
> allow additional D-PHY register configurations after enabling data and
> clock lanes. This is required for the RZ/V2H(P) SoC but not for the
> RZ/G2L SoC.
>
> Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined,
> ensuring SoC-specific initialization is performed only when necessary.
>
> This change prepares for RZ/V2H(P) SoC support while maintaining
> compatibility with existing platforms.
>
> Co-developed-by: Fabrizio Castro <fabrizio.castro...@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro...@renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das...@bp.renesas.com>
> ---
> v4->v5:
> - Added Reviewed tag from Biju
>
> v3->v4:
> - No changes
>
> v2->v3:
> - No changes
>
> v1->v2:
> - No changes
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 55a1c1b043c8..e1ce21a9ddb3 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -34,6 +34,7 @@ struct rzg2l_mipi_dsi;
>
> struct rzg2l_mipi_dsi_hw_info {
> int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
> + void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi);
As this is called at startup time I would have called it dphy_startup.
Up to you.
Reviewed-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
> void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
> u32 phy_reg_offset;
> u32 link_reg_offset;
> @@ -320,6 +321,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi
> *dsi,
> txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
> rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
>
> + if (dsi->info->dphy_late_init)
> + dsi->info->dphy_late_init(dsi);
> +
> hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
> /*
> * Global timings characteristic depends on high speed Clock Frequency
--
Regards,
Laurent Pinchart
