On Wed, May 14, 2025 at 05:10:34PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
>
> Make the values a bit more meaningful.
Not sure if it's more meaningful or not. In the end, we all can read hex
masks.
>
> Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
> ---
> drivers/soc/qcom/ubwc_config.c | 33 +++++++++++++++++++++------------
> include/linux/soc/qcom/ubwc.h | 2 ++
> 2 files changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> index
> 96b94cf01218cce2dacdba22c7573ba6148fcdd1..06ddf78eb08d31bcdd11f23dcf9ff32e390d2eff
> 100644
> --- a/drivers/soc/qcom/ubwc_config.c
> +++ b/drivers/soc/qcom/ubwc_config.c
> @@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = {
> static const struct qcom_ubwc_cfg_data sa8775p_data = {
> .ubwc_enc_version = UBWC_4_0,
> .ubwc_dec_version = UBWC_4_0,
> - .ubwc_swizzle = 4,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> .highest_bank_bit = 13,
> .macrotile_mode = true,
> @@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = {
> static const struct qcom_ubwc_cfg_data sar2130p_data = {
> .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
> .ubwc_dec_version = UBWC_4_3,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> .highest_bank_bit = 13,
> .macrotile_mode = true,
> @@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = {
> static const struct qcom_ubwc_cfg_data sc7180_data = {
> .ubwc_enc_version = UBWC_2_0,
> .ubwc_dec_version = UBWC_2_0,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> .highest_bank_bit = 14,
> };
> @@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data = {
> static const struct qcom_ubwc_cfg_data sc7280_data = {
> .ubwc_enc_version = UBWC_3_0,
> .ubwc_dec_version = UBWC_4_0,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> .highest_bank_bit = 14,
> .macrotile_mode = true,
> @@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = {
> static const struct qcom_ubwc_cfg_data sc8280xp_data = {
> .ubwc_enc_version = UBWC_4_0,
> .ubwc_dec_version = UBWC_4_0,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> .highest_bank_bit = 16,
> .macrotile_mode = true,
> @@ -95,7 +99,7 @@ static const struct qcom_ubwc_cfg_data sdm845_data = {
> static const struct qcom_ubwc_cfg_data sm6115_data = {
> .ubwc_enc_version = UBWC_1_0,
> .ubwc_dec_version = UBWC_2_0,
> - .ubwc_swizzle = 7,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_ALL,
> .ubwc_bank_spread = true,
> .highest_bank_bit = 14,
> };
> @@ -103,7 +107,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data = {
> static const struct qcom_ubwc_cfg_data sm6125_data = {
> .ubwc_enc_version = UBWC_1_0,
> .ubwc_dec_version = UBWC_3_0,
> - .ubwc_swizzle = 7,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_ALL,
> .highest_bank_bit = 14,
> };
>
> @@ -116,7 +120,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data = {
> static const struct qcom_ubwc_cfg_data sm6350_data = {
> .ubwc_enc_version = UBWC_2_0,
> .ubwc_dec_version = UBWC_2_0,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> .highest_bank_bit = 14,
> };
> @@ -136,7 +141,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data = {
> static const struct qcom_ubwc_cfg_data sm8250_data = {
> .ubwc_enc_version = UBWC_4_0,
> .ubwc_dec_version = UBWC_4_0,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> /* TODO: highest_bank_bit = 15 for LP_DDR4 */
> .highest_bank_bit = 16,
> @@ -146,7 +152,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data = {
> static const struct qcom_ubwc_cfg_data sm8350_data = {
> .ubwc_enc_version = UBWC_4_0,
> .ubwc_dec_version = UBWC_4_0,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> /* TODO: highest_bank_bit = 15 for LP_DDR4 */
> .highest_bank_bit = 16,
> @@ -156,7 +163,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data = {
> static const struct qcom_ubwc_cfg_data sm8550_data = {
> .ubwc_enc_version = UBWC_4_0,
> .ubwc_dec_version = UBWC_4_3,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> /* TODO: highest_bank_bit = 15 for LP_DDR4 */
> .highest_bank_bit = 16,
> @@ -166,7 +174,8 @@ static const struct qcom_ubwc_cfg_data sm8550_data = {
> static const struct qcom_ubwc_cfg_data x1e80100_data = {
> .ubwc_enc_version = UBWC_4_0,
> .ubwc_dec_version = UBWC_4_3,
> - .ubwc_swizzle = 6,
> + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
> + UBWC_SWIZZLE_ENABLE_LVL(3),
> .ubwc_bank_spread = true,
> /* TODO: highest_bank_bit = 15 for LP_DDR4 */
> .highest_bank_bit = 16,
> diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
> index
> 30d9744c5d2e06d4aa93b64f7d2bc0e855c7a10b..2a12e054ec62ae7e76c3f3291d6963da726eee4f
> 100644
> --- a/include/linux/soc/qcom/ubwc.h
> +++ b/include/linux/soc/qcom/ubwc.h
> @@ -26,6 +26,8 @@ struct qcom_ubwc_cfg_data {
> * controls level 2, and BIT(2) enables level 3.
> */
> u32 ubwc_swizzle;
> +#define UBWC_SWIZZLE_ENABLE_ALL GENMASK(2, 0)
> +#define UBWC_SWIZZLE_ENABLE_LVL(n) BIT(((n) - 1))
>
> /**
> * @highest_bank_bit: Highest Bank Bit
>
> --
> 2.49.0
>
--
With best wishes
Dmitry
