[PATCH RFT v2 10/15] drm/msm/a6xx: Simplify min_acc_len calculation

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>

It's only necessary for some lower end parts.
Also rename it to min_acc_len_64b to denote that if set, the minimum
access length is 64 bits, 32b otherwise.

Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 
5ee5f8dc90fe0d1647ce07b7dbcadc6ca2ecd416..fdc843c47c075a92ec8305217c355e4ccee876dc
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -592,14 +592,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
        if (IS_ERR(gpu->common_ubwc_cfg))
                return -EINVAL;
 
-       gpu->ubwc_config.min_acc_len = 0;
        gpu->ubwc_config.ubwc_swizzle = 0x6;
        gpu->ubwc_config.macrotile_mode = 0;
        gpu->ubwc_config.highest_bank_bit = 15;
 
        if (adreno_is_a610(gpu)) {
                gpu->ubwc_config.highest_bank_bit = 13;
-               gpu->ubwc_config.min_acc_len = 1;
                gpu->ubwc_config.ubwc_swizzle = 0x7;
        }
 
@@ -645,10 +643,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
                gpu->ubwc_config.macrotile_mode = 1;
        }
 
-       if (adreno_is_a702(gpu)) {
+       if (adreno_is_a702(gpu))
                gpu->ubwc_config.highest_bank_bit = 14;
-               gpu->ubwc_config.min_acc_len = 1;
-       }
 
        return 0;
 }
@@ -657,6 +653,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
        u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || 
adreno_is_a7xx(adreno_gpu) ? 2 : 0;
+       bool min_acc_len_64b = adreno_is_a610(adreno_gpu) || 
adreno_is_a702(adreno_gpu);
        const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
        /*
         * We subtract 13 from the highest bank bit (13 is the minimum value
@@ -676,18 +673,18 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
                  level2_swizzling_dis << 12 |
                  rgb565_predicator << 11 |
                  hbb_hi << 10 | amsbc << 4 |
-                 adreno_gpu->ubwc_config.min_acc_len << 3 |
+                 min_acc_len_64b << 3 |
                  hbb_lo << 1 | ubwc_mode);
 
        gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
                  level2_swizzling_dis << 6 | hbb_hi << 4 |
-                 adreno_gpu->ubwc_config.min_acc_len << 3 |
+                 min_acc_len_64b << 3 |
                  hbb_lo << 1 | ubwc_mode);
 
        gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
                  level2_swizzling_dis << 12 | hbb_hi << 10 |
                  uavflagprd_inv << 4 |
-                 adreno_gpu->ubwc_config.min_acc_len << 3 |
+                 min_acc_len_64b << 3 |
                  hbb_lo << 1 | ubwc_mode);
 
        if (adreno_is_a7xx(adreno_gpu))
@@ -695,7 +692,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
                          FIELD_PREP(GENMASK(8, 5), hbb_lo));
 
        gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
-                 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21);
+                 min_acc_len_64b << 23 | hbb_lo << 21);
 
        gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
                  adreno_gpu->ubwc_config.macrotile_mode);

-- 
2.49.0