On 10/16/25 4:28 AM, Liu Ying wrote:
Hello Liu,
Have you got i.MX95 DC IP spec? If no, then it would be difficult for you to
write DT bindings for all i.MX95 DC units. Note that this is something
necessary to do.
Nope, still waiting for those.
And, a bit more information about display pipelines in i.MX95 display domain:
Dither -> pixel interleaver -> pixel link loopback -> camera domain
-> pixel link -> MIPI DSI controller
-> pixel mapper(LDB)
Note that NXP downstream kernel wrongly adds pixel link between pixel
interleaver and pixel mapper due to ambiguous i.MX95 TRM.
Is my understanding correct, that the Dither Unit ~= Display Engine ?
