On 10/17/25, Marek Vasut <[email protected]> wrote: > On 10/16/25 4:28 AM, Liu Ying wrote: > > Hello Liu,
Hello Marek, > > > Have you got i.MX95 DC IP spec? If no, then it would be difficult for you > > to > > write DT bindings for all i.MX95 DC units. Note that this is something > > necessary to do. > > Nope, still waiting for those. > > > And, a bit more information about display pipelines in i.MX95 display > domain: > > > > Dither -> pixel interleaver -> pixel link loopback -> camera domain > > -> pixel link -> MIPI DSI controller > > -> pixel mapper(LDB) > > > > Note that NXP downstream kernel wrongly adds pixel link between pixel > > interleaver and pixel mapper due to ambiguous i.MX95 TRM. > Is my understanding correct, that the Dither Unit ~= Display Engine ? Nope, Dither Unit is a component of Display Engine. You may take a look at fsl,imx8qxp-dc-display-engine.yaml whose patternProperties lists all components of i.MX8qxp DC Display Engine and Dither Unit is one of them. i.MX95 DC Display Engine has below components: Domain Blend Unit, Frame Generator, Color Matrix, LUT 3D, Dither Unit, from the first input component to the last output component, and additionally, Signature Unit and IDHash Unit which be configured to tap from some of the above components. Liu Ying
