On 2/25/26 6:45 AM, Pengyu Luo wrote:
> The DT configuration follows other Samsung 5nm-based Qualcomm SOCs,
> utilizing the same register layouts and clock structures.
>
> However, DSI won't work properly for now (Partial content wrapped to
> the left side) until we submit dispcc fixes. And some panels require
> DPU timing calculation fixes too. (hdisplay / width timing round errors
> cause the fifo error)
>
> Co-developed-by: Tianyu Gao <[email protected]>
> Signed-off-by: Tianyu Gao <[email protected]>
> Signed-off-by: Pengyu Luo <[email protected]>
> Tested-by: White Lewis <[email protected]> # HUAWEI Gaokun3
> ---
[...]
> + port@1 {
> + reg = <1>;
> + mdss0_intf1_out: endpoint {
style: it's preferable to keep a new line between the last property and the
following subnode, i.e.:
port@1 {
reg = <1>;
mdss0_intf1_out: endpoint {
...
}
> + remote-endpoint =
> <&mdss0_dsi0_in>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + mdss0_intf2_out: endpoint {
> + remote-endpoint =
> <&mdss0_dsi1_in>;
> + };
> + };
> +
> port@4 {
> reg = <4>;
> mdss0_intf4_out: endpoint {
> @@ -4791,6 +4806,195 @@ opp-810000000 {
[...]
> + phy-names = "dsi";
> +
> + phys = <&mdss0_dsi0_phy>;
property
property-names
in this order, please
[...]
> + mdss0_dsi0_phy: phy@ae94400 {
> + compatible = "qcom,sc8280xp-dsi-phy-5nm";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x27c>;
last entry: size=0x280, all instances, there's actually a register at +0x27c
[...]
> + mdss0_dsi1_opp_table: opp-table {
You can reference the prior OPP table (and just call it dsi_opp_table)
since they're identical
Konrad
