On Wed, Feb 25, 2026 at 01:45:25PM +0800, Pengyu Luo wrote: > The DT configuration follows other Samsung 5nm-based Qualcomm SOCs, > utilizing the same register layouts and clock structures. > > However, DSI won't work properly for now (Partial content wrapped to > the left side) until we submit dispcc fixes. And some panels require > DPU timing calculation fixes too. (hdisplay / width timing round errors > cause the fifo error)
I'm looking forward to reviewing those patches! > -- With best wishes Dmitry
