On 2026-02-25, Gary Guo <[email protected]> wrote: > On 2026-02-24 22:53, Joel Fernandes wrote: >> +//! ## MMU v2 (Turing/Ampere/Ada) - 5 levels >> [...] >> +//! ## MMU v3 (Hopper+) - 6 levels > > I think this is called "4 levels" and "5 levels" in kernel MM rather than > "5 levels" and "6 levels".
Actually, I think "5 levels" and "6 levels" is correct even by x86 kernel MM convention. In x86 "4-level paging", the 4 levels are PGD, PUD, PMD, PTE - the root page directory (PGD) IS counted as one of the 4 levels. Similarly, for the GPU MMU, counting the root PDB (L0) as a level gives us 5 levels for v2 (PDB/L0 through L4/PTE) and 6 levels for v3 (PDB/L0 through L5/PTE). This is also consistent with NVIDIA's own hardware definitions in the OpenRM headers (dev_mmu.h for Turing and Hopper) which define the page table entries for each of these levels. The virtual address bitfield spans L0 (bits 56:48) through L4 (bits 20:12) for v2, giving 5 distinct page table levels. FWIW, the existing nouveau driver also uses this convention - NVKM_VMM_LEVELS_MAX is defined as 6 in nvkm/subdev/mmu/vmm.c, and the GH100 page table descriptors in vmmgh100.c list all 6 levels. -- Joel Fernandes
