On 3/6/26 5:47 PM, Dmitry Baryshkov wrote:
> The UBWC registers in the MDSS region are not dependent on the UBWC
> version (it is an invalid assumption we inherited from the vendor SDE
> driver). Instead they are dependent only on the MDSS core revision.
>
> Rework UBWC programming to follow MDSS revision and to use required (aka
> encoder) UBWC version instead of the ubwc_dec_version.
>
> Fixes: d68db6069a8e ("drm/msm/mdss: convert UBWC setup to use match data")
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 120
> ++++++++++++++++-------------------------
> 1 file changed, 45 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 9047e8d9ee89..9f81f43283b9 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -166,27 +166,27 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss
> *msm_mdss)
> return 0;
> }
>
> -static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
> +static void msm_mdss_setup_ubwc_v4(struct msm_mdss *msm_mdss)
> {
> const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
> - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
> + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
The field takes bit0/1/2 for *enabling* level 1/2/3 swizzling - is this
intended?
[...]
> +static void msm_mdss_setup_ubwc_v5(struct msm_mdss *msm_mdss)
> {
> const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
> - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
> + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
> MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit -
> 13);
>
> + if (data->ubwc_bank_spread)
> + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
8250 is ubwcv4 (in our catalog anyway) and definitely has a bit for this
Konrad
