Convert the JOB_CONTROL register definitions to use the `register!` macro. Using the `register!` macro allows us to replace manual bit masks and shifts with typed register and field accessors, which makes the code easier to read and avoids errors from bit manipulation.
Co-developed-by: Daniel Almeida <[email protected]> Signed-off-by: Daniel Almeida <[email protected]> Signed-off-by: Deborah Brouwer <[email protected]> --- drivers/gpu/drm/tyr/regs.rs | 58 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs index ba61a3dbe2a3e6fa1169b03d4f62e82769041057..686986536297ac2cc53ff14b162b19eaa759c192 100644 --- a/drivers/gpu/drm/tyr/regs.rs +++ b/drivers/gpu/drm/tyr/regs.rs @@ -28,7 +28,6 @@ #![allow(dead_code)] use kernel::{ - bits::bit_u32, device::{ Bound, Device, // @@ -628,14 +627,57 @@ impl MCU_STATUS { pub(super) use gpu_control::*; -pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register; -pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register; -pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register; -pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register; - -pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31); - pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register; pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register; pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register; pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register; + +/// These registers correspond to the JOB_CONTROL register page. +/// They are involved in communication between the firmware running on the MCU and the host. +pub(super) mod job_control { + use kernel::register; + + register! { + /// Raw status of job interrupts. + /// + /// Write to this register to trigger these interrupts. + /// Writing a 1 to a bit forces that bit on. + pub(crate) JOB_IRQ_RAWSTAT(u32) @ 0x1000 { + /// CSG request. These bits indicate that CSGn requires attention from the host. + 30:0 csg; + /// GLB request. Indicates that the GLB interface requires attention from the host. + 31:31 glb; + } + + /// Clear job interrupts. Write only. + /// + /// Write a 1 to a bit to clear the corresponding bit in [`JOB_IRQ_RAWSTAT`]. + pub(crate) JOB_IRQ_CLEAR(u32) @ 0x1004 { + /// Clear CSG request interrupts. + 30:0 csg; + /// Clear GLB request interrupt. + 31:31 glb; + } + + /// Mask for job interrupts. + /// + /// Set each bit to 1 to enable the corresponding interrupt source or to 0 to disable it. + pub(crate) JOB_IRQ_MASK(u32) @ 0x1008 { + /// Enable CSG request interrupts. + 30:0 csg; + /// Enable GLB request interrupt. + 31:31 glb; + } + + /// Active job interrupts. Read only. + /// + /// This register contains the result of ANDing together [`JOB_IRQ_RAWSTAT`] and + /// [`JOB_IRQ_MASK`]. + pub(crate) JOB_IRQ_STATUS(u32) @ 0x100c { + /// CSG request interrupt status. + 30:0 csg; + /// GLB request interrupt status. + 31:31 glb; + } + } +} -- 2.52.0
