Move the defines around and rename for clarity and consistency. No functional change.
Signed-off-by: Tomi Valkeinen <[email protected]> --- drivers/gpu/drm/bridge/tc358762.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c index 98df3e667d4a..833fd9913c75 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -29,17 +29,22 @@ /* PPI layer registers */ #define PPI_STARTPPI 0x0104 /* START control bit */ +#define PPI_STARTPPI_STARTPPI BIT(0) + #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ #define PPI_D0S_ATMR 0x0144 #define PPI_D1S_ATMR 0x0148 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ -#define PPI_START_FUNCTION 1 /* DSI layer registers */ #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ +#define DSI_STARTDSI_STARTDSI BIT(0) + #define DSI_LANEENABLE 0x0210 /* Enables each lane */ -#define DSI_RX_START 1 +#define DSI_LANEENABLE_CLEN BIT(0) +#define DSI_LANEENABLE_L0EN BIT(1) +#define DSI_LANEENABLE_L1EN BIT(2) /* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 */ #define LCDCTRL 0x0420 /* Video Path Control */ @@ -60,14 +65,8 @@ /* System Controller Registers */ #define SYSCTRL 0x0464 -/* System registers */ #define LPX_PERIOD 3 -/* Lane enable PPI and DSI register bits */ -#define LANEENABLE_CLEN BIT(0) -#define LANEENABLE_L0EN BIT(1) -#define LANEENABLE_L1EN BIT(2) - struct tc358762 { struct device *dev; struct drm_bridge bridge; @@ -118,7 +117,7 @@ static int tc358762_init(struct tc358762 *ctx) u32 lcdctrl; tc358762_write(ctx, DSI_LANEENABLE, - LANEENABLE_L0EN | LANEENABLE_CLEN); + DSI_LANEENABLE_L0EN | DSI_LANEENABLE_CLEN); tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5); tc358762_write(ctx, PPI_D0S_ATMR, 0); @@ -141,8 +140,8 @@ static int tc358762_init(struct tc358762 *ctx) tc358762_write(ctx, SYSCTRL, 0x040f); msleep(100); - tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); - tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START); + tc358762_write(ctx, PPI_STARTPPI, PPI_STARTPPI_STARTPPI); + tc358762_write(ctx, DSI_STARTDSI, DSI_STARTDSI_STARTDSI); msleep(100); -- 2.43.0
