Update comment about the number of lanes.
Signed-off-by: Tomi Valkeinen <[email protected]>
---
drivers/gpu/drm/bridge/tc358762.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/tc358762.c
b/drivers/gpu/drm/bridge/tc358762.c
index 7840ab3454f6..c5734c4df440 100644
--- a/drivers/gpu/drm/bridge/tc358762.c
+++ b/drivers/gpu/drm/bridge/tc358762.c
@@ -306,7 +306,14 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
ctx->dev = dev;
ctx->pre_enabled = false;
- /* TODO: Find out how to get dual-lane mode working */
+ /*
+ * When using DSI clk for pixel clock (only mode supported in the
driver),
+ * the pclk is derived directly from the DSI byteclk via simple divider,
+ * which is either 2 or 3.
+ * The required divider can be calculated with bitspp / 8 / nlanes.
Thus,
+ * for RGB888, only nlanes = 1 works as nlanes = 2 would require divider
+ * of 1.5.
+ */
dsi->lanes = 1;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
--
2.43.0
