LCDCTRL fields are quite wrong in the driver. Fix the field defines. A few notes about the wrong fields:
LCDCTRL_VSDELAY(1) actually sets LCDCTRL_DCLK_POL LCDCTRL_UNK6 | LCDCTRL_VTGEN actually set LCDCTRL_PXLFORM_RGB888 LCDCTRL_RGB888 actually sets LCDCTRL_DPI_EN The total still resulted in a working display even if the defines were quite wrong. Signed-off-by: Tomi Valkeinen <[email protected]> --- drivers/gpu/drm/bridge/tc358762.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c index c8b9984ff301..669052074974 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -47,17 +47,22 @@ #define DSI_LANEENABLE_L0EN BIT(1) #define DSI_LANEENABLE_L1EN BIT(2) -/* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 */ +/* LCDC/DPI Registers */ #define LCDCTRL 0x0420 /* Video Path Control */ #define LCDCTRL_MSF BIT(0) /* Magic square in RGB666 */ -#define LCDCTRL_VTGEN BIT(4)/* Use chip clock for timing */ -#define LCDCTRL_UNK6 BIT(6) /* Unknown */ -#define LCDCTRL_EVTMODE BIT(5) /* Event mode */ -#define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */ -#define LCDCTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ -#define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */ -#define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ -#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */ +#define LCDCTRL_VTGEN BIT(1) /* Use chip clock for timing */ +#define LCDCTRL_PXLFORM GENMASK_U32(6, 4) +#define LCDCTRL_PXLFORM_RGB666 0 /* x:R:G:B 6:8:8:8 */ +#define LCDCTRL_PXLFORM_RGB666_24 1 /* x:R:x:G:x:B 2:6:2:6:2:6 */ +#define LCDCTRL_PXLFORM_RGB565 2 /* x:R:G:B 8:5:6:5 */ +#define LCDCTRL_PXLFORM_RGB565_1 3 /* x:R:x:G:x:B 3:5:2:6:3:5 */ +#define LCDCTRL_PXLFORM_RGB565_2 4 /* x:R:x:G:x:B:x 2:5:3:6:2:5:1 */ +#define LCDCTRL_PXLFORM_RGB888 5 /* R:G:B 8:8:8 */ +#define LCDCTRL_DPI_EN BIT(8) +#define LCDCTRL_HSYNC_POL BIT(17) /* Polarity of HSYNC signal */ +#define LCDCTRL_DE_POL BIT(18) /* Polarity of DE signal */ +#define LCDCTRL_VSYNC_POL BIT(19) /* Polarity of VSYNC signal */ +#define LCDCTRL_DCLK_POL BIT(20) /* Polarity of pixel clock */ /* SPI Master Registers */ #define SPICMR 0x0450 @@ -140,14 +145,16 @@ static int tc358762_init(struct tc358762 *ctx) tc358762_write(ctx, SPICMR, 0x00); - lcdctrl = LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 | - LCDCTRL_UNK6 | LCDCTRL_VTGEN; + lcdctrl = FIELD_PREP(LCDCTRL_PXLFORM, LCDCTRL_PXLFORM_RGB888) | + LCDCTRL_DPI_EN; + + lcdctrl |= LCDCTRL_DCLK_POL; if (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC) - lcdctrl |= LCDCTRL_HSPOL; + lcdctrl |= LCDCTRL_HSYNC_POL; if (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC) - lcdctrl |= LCDCTRL_VSPOL; + lcdctrl |= LCDCTRL_VSYNC_POL; tc358762_write(ctx, LCDCTRL, lcdctrl); -- 2.43.0
