The driver hardcodes LCDCTRL_DCLK_POL and ~DE_POL, ignoring what the panel actuall wants. Fix this by looking at the bridge_state->output_bus_cfg.flags, and set the polarities correctly.
Signed-off-by: Tomi Valkeinen <[email protected]> --- drivers/gpu/drm/bridge/tc358762.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c index 47ae706de4cb..92e7e2ade942 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -187,12 +187,15 @@ static void tc358762_enable(struct drm_bridge *bridge, { struct tc358762 *ctx = bridge_to_tc358762(bridge); struct drm_connector_state *conn_state; + struct drm_bridge_state *bridge_state; struct drm_crtc_state *crtc_state; struct drm_connector *connector; struct drm_display_mode *mode; u32 lcdctrl; int ret; + bridge_state = drm_atomic_get_new_bridge_state(state, bridge); + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); conn_state = drm_atomic_get_new_connector_state(state, connector); crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); @@ -244,7 +247,9 @@ static void tc358762_enable(struct drm_bridge *bridge, if (ctx->use_vtg) lcdctrl |= LCDCTRL_VTGEN; - lcdctrl |= LCDCTRL_DCLK_POL; + /* Note: DCLK_POL affects pixdata, de and syncs */ + if (bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) + lcdctrl |= LCDCTRL_DCLK_POL; if (mode->flags & DRM_MODE_FLAG_PHSYNC) lcdctrl |= LCDCTRL_HSYNC_POL; @@ -252,6 +257,9 @@ static void tc358762_enable(struct drm_bridge *bridge, if (mode->flags & DRM_MODE_FLAG_PVSYNC) lcdctrl |= LCDCTRL_VSYNC_POL; + if (bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW) + lcdctrl |= LCDCTRL_DE_POL; + tc358762_write(ctx, LCDCTRL, lcdctrl); tc358762_write(ctx, PPI_STARTPPI, PPI_STARTPPI_STARTPPI); -- 2.43.0
