On Thu, May 07, 2026 at 11:21:30AM +0200, Tommaso Merciai wrote:
> The RZ/G3E SoC integrates two LCD controllers (LCDC0 and LCDC1), each
> containing a FCPVD, VSPD, and Display Unit (DU).
>
> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
>
> Add compatible string 'renesas,r9a09g047-du' and extend the binding to
> support two DU instances: add reg-names ('du0'/'du1'), extend reg,
> interrupts, and resets to maxItems: 2, and extend clocks/clock-names to
> six entries (aclk/pclk/vclk per instance, minItems: 3).
Don't write what the diff has. I can read the diff for that.
>
> Drop the "Each port shall have a single endpoint." constraint since
> RZ/G3E ports expose multiple endpoints.
>
> Add a RZ/G3E-specific allOf rule mapping two DU instances to two ports:
>
> - port@0 (DU0): endpoint@0 DSI, endpoint@2 LVDS ch0, endpoint@3 LVDS ch1
> - port@1 (DU1): endpoint@0 DSI, endpoint@1 RGB (DPAD), endpoint@3 LVDS ch1
>
> Signed-off-by: Tommaso Merciai <[email protected]>
> ---
> v6->v7:
> - Rebased on top of [1]
> [1]
> https://lore.kernel.org/all/[email protected]/
> - Use single DRM device aggregating both DU instances (1 DU dt node),
> modelling single port for each DU0, DU1 and multiple endpoints for
> outputs.
That seems like the completely wrong thing to do and you've given no
reason why you think it is the right choice.
Rob
