The DCLK parent switch logic for HDMI0 and HDMI1 PHY PLLs was duplicated, with each endpoint repeating the same clk_get_parent(), clk_set_parent() and error handling calls.
Refactor this by first selecting the appropriate PHY PLL clock handle based on the active HDMI endpoint, then performing the parent switch in a single shared code path. Signed-off-by: Cristian Ciocaltea <[email protected]> --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 36 +++++++++++----------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 17d21e08ad97..df475173dc8e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1932,42 +1932,34 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, unsigned int bpc = vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV422 ? 8 : vcstate->output_bpc; unsigned long max_dclk = DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8, bpc); + struct clk *pll_hdmiphy = NULL; if (clock <= max_dclk) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { - if (!vop2->pll_hdmiphy0) - break; - - if (!vp->dclk_src) - vp->dclk_src = clk_get_parent(vp->dclk); - - ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI0 PHY PLL: %d\n", - ret); + pll_hdmiphy = vop2->pll_hdmiphy0; break; } if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { - if (!vop2->pll_hdmiphy1) - break; - - if (!vp->dclk_src) - vp->dclk_src = clk_get_parent(vp->dclk); - - ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); - if (ret < 0) - drm_warn(vop2->drm, - "Could not switch to HDMI1 PHY PLL: %d\n", - ret); + pll_hdmiphy = vop2->pll_hdmiphy1; break; } } } + + if (pll_hdmiphy) { + if (!vp->dclk_src) + vp->dclk_src = clk_get_parent(vp->dclk); + + ret = clk_set_parent(vp->dclk, pll_hdmiphy); + if (ret < 0) + drm_warn(vop2->drm, + "Failed to switch DCLK to HDMI PHY PLL: %d\n", + ret); + } } clk_set_rate(vp->dclk, clock); -- 2.54.0
