Rockchip DW HDMI QP encoder supports YUV 4:2:2 output through ROCKCHIP_OUT_MODE_YUV422, but was limited to 8-bit depth via MEDIA_BUS_FMT_UYVY8_1X16. Add support for its 10-bit counterpart MEDIA_BUS_FMT_UYVY10_1X20, which carries two 10-bit components per clock cycle on a 20-bit wide bus.
YUV 4:2:2 always transmits two 12-bit components per pixel, regardless of the color depth. From a clock-rate perspective this is equivalent to three 8-bit RGB components, so configure the HDMI PHY with 8 bpc when YUV 4:2:2 is in use to keep its output clock aligned with the TMDS character rate. Otherwise the PHY PLL output would be scaled by bpc/8 for higher color depths, producing a clock rate that confuses downstream consumers such as the VOP2 display controller. Signed-off-by: Cristian Ciocaltea <[email protected]> --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c index 815f9ea7bcbe..3a1c027aa90b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -216,6 +216,7 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder, s->output_mode = ROCKCHIP_OUT_MODE_AAAA; break; case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_UYVY10_1X20: s->output_mode = ROCKCHIP_OUT_MODE_YUV422; break; case MEDIA_BUS_FMT_UYYVYY8_0_5X24: @@ -227,7 +228,14 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder, } phy_cfg.hdmi.tmds_char_rate = conn_state->hdmi.tmds_char_rate; - phy_cfg.hdmi.bpc = conn_state->hdmi.output_bpc; + /* + * YUV422 always transmits two 12-bit components per clock cycle, + * regardless of the color depth, which from a rate perspective is + * equivalent to three 8-bit RGB components. Force 8 bpc here to + * keep the PHY PLL output aligned with the TMDS character rate. + */ + phy_cfg.hdmi.bpc = (s->output_mode == ROCKCHIP_OUT_MODE_YUV422 ? + 8 : conn_state->hdmi.output_bpc); ret = phy_configure(hdmi->phy, &phy_cfg); if (!ret) { -- 2.54.0
