Add DU node to RZ/G3E SoC DTSI.
Signed-off-by: Tommaso Merciai <[email protected]>
---
v7->v8
- New patch.
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 52 ++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 73757e8e2197..4f95b0d7e8ab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -2105,6 +2105,58 @@ csi2cru: endpoint@0 {
};
};
+ du: display@16460000 {
+ compatible = "renesas,r9a09g047-du";
+ reg = <0 0x16460000 0 0x10000>,
+ <0 0x16490000 0 0x10000>;
+ reg-names = "du.0", "du.1";
+ interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "du.0", "du.1";
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>,
+ <&cpg CPG_MOD 0x1a8>,
+ <&cpg CPG_MOD 0x1a9>,
+ <&cpg CPG_MOD 0x1aa>;
+ clock-names = "aclk", "pclk", "vclk",
+ "aclk1", "pclk1", "vclk1";
+ resets = <&cpg 0xdc>, <&cpg 0x11e>;
+ reset-names = "resetn", "resetn1";
+ power-domains = <&cpg>;
+ renesas,vsps = <&vspd0 0>, <&vspd1 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du_out_rgb: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ du_out_lvds0: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ du_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+
fcpvd0: fcp@16470000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
--
2.54.0
