Raise the CRTC and VSP limits to two and create one CRTC per bit set in the channels_mask of the SoC information, mapping the software CRTC index to the hardware channel index.
All currently supported SoCs have a single DU channel, so there is no functional change for them. Signed-off-by: Tommaso Merciai <[email protected]> --- v7->v8 - New patch. drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++-- drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 14 +++++++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h index 3a649fd438e0..cb9ad869d66b 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -59,8 +59,8 @@ struct rzg2l_du_device_info { unsigned int features; }; -#define RZG2L_DU_MAX_CRTCS 1 -#define RZG2L_DU_MAX_VSPS 1 +#define RZG2L_DU_MAX_CRTCS 2 +#define RZG2L_DU_MAX_VSPS 2 #define RZG2L_DU_MAX_DSI 1 struct rzg2l_du_device { diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c index 7cbdf146788e..04f51b9d1dd8 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c @@ -405,6 +405,8 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu) struct drm_device *dev = &rcdu->ddev; struct drm_encoder *encoder; unsigned int num_encoders; + unsigned int swindex; + unsigned int hwindex; int ret; ret = drmm_mode_config_init(dev); @@ -440,9 +442,15 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu) return ret; /* Create the CRTCs. */ - ret = rzg2l_du_crtc_create(rcdu, 0, 0); - if (ret < 0) - return ret; + for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) { + /* Skip unpopulated DU channels. */ + if (!(rcdu->info->channels_mask & BIT(hwindex))) + continue; + + ret = rzg2l_du_crtc_create(rcdu, swindex++, hwindex); + if (ret < 0) + return ret; + } /* Initialize the encoders. */ ret = rzg2l_du_encoders_init(rcdu); -- 2.54.0
