In preparation for SoCs that integrate several DU channels, pass the software and hardware channel indices to rzg2l_du_crtc_create().
The single caller is updated to pass zero for both indices, so there is no functional change. Signed-off-by: Tommaso Merciai <[email protected]> --- v7->v8 - New patch. drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 15 ++++++++------- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h | 3 ++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 2 +- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c index 3e82a0a2014a..5aecf325e89b 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -377,10 +377,11 @@ static const struct drm_crtc_funcs crtc_funcs_rz = { * Initialization */ -int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu) +int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu, unsigned int swindex, + unsigned int hwindex) { struct platform_device *pdev = to_platform_device(rcdu->dev); - struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0]; + struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[swindex]; struct drm_crtc *crtc = &rcrtc->crtc; struct drm_plane *primary; int ret; @@ -388,31 +389,31 @@ int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu) /* I/O resources */ rcrtc->mmio = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rcrtc->mmio)) { - dev_err(rcdu->dev, "failed to map MMIO for DU\n"); + dev_err(rcdu->dev, "failed to map MMIO for DU%u\n", hwindex); return PTR_ERR(rcrtc->mmio); } rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, NULL); if (IS_ERR(rcrtc->rstc)) { - dev_err(rcdu->dev, "can't get cpg reset\n"); + dev_err(rcdu->dev, "can't get cpg reset for DU%u\n", hwindex); return PTR_ERR(rcrtc->rstc); } rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk"); if (IS_ERR(rcrtc->rzg2l_clocks.aclk)) { - dev_err(rcdu->dev, "no axi clock for DU\n"); + dev_err(rcdu->dev, "no axi clock for DU%u\n", hwindex); return PTR_ERR(rcrtc->rzg2l_clocks.aclk); } rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk"); if (IS_ERR(rcrtc->rzg2l_clocks.pclk)) { - dev_err(rcdu->dev, "no peripheral clock for DU\n"); + dev_err(rcdu->dev, "no peripheral clock for DU%u\n", hwindex); return PTR_ERR(rcrtc->rzg2l_clocks.pclk); } rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { - dev_err(rcdu->dev, "no video clock for DU\n"); + dev_err(rcdu->dev, "no video clock for DU%u\n", hwindex); return PTR_ERR(rcrtc->rzg2l_clocks.dclk); } diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h index 77ec92c4825d..0fa8c4369851 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h @@ -84,7 +84,8 @@ static inline struct rzg2l_du_crtc_state *to_rzg2l_crtc_state(struct drm_crtc_st return container_of(s, struct rzg2l_du_crtc_state, state); } -int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu); +int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu, unsigned int swindex, + unsigned int hwindex); void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc); diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c index 87f171145a23..7cbdf146788e 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c @@ -440,7 +440,7 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu) return ret; /* Create the CRTCs. */ - ret = rzg2l_du_crtc_create(rcdu); + ret = rzg2l_du_crtc_create(rcdu, 0, 0); if (ret < 0) return ret; -- 2.54.0
