From: Ritesh Kumar <[email protected]> Nord requires BIAS_EN_CLKBUFLR_EN to be set to 0x1f to enable the internal bias generator and clock buffer, which differs from the value used on existing SoCs. Add qcom_edp_com_bias_en_clkbuflr_nord() per HPG Table 2-1-d.
Signed-off-by: Ritesh Kumar <[email protected]> Signed-off-by: Nabige Aala <[email protected]> --- drivers/phy/qualcomm/phy-qcom-edp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 6cac4b55b66f..ec4220cffe69 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -1637,6 +1637,14 @@ static int qcom_edp_phy_com_resetsm_cntrl_nord(const struct qcom_edp *edp) } +static int qcom_edp_com_bias_en_clkbuflr_nord(const struct qcom_edp *edp) +{ + writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + + return 0; +} + + static const struct of_device_id qcom_edp_phy_match_table[] = { { .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, }, { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, }, -- 2.34.1
