From: Ritesh Kumar <[email protected]> Nord requires different LDO levels, TX lane control offsets and TX resistor calibration codes compared to existing SoCs. Add qcom_edp_ldo_config_nord(), qcom_edp_phy_tx_lane_cfg_nord() and qcom_edp_phy_tx_res_cfg_nord() with values per HPG Table 2-1-d.
Signed-off-by: Ritesh Kumar <[email protected]> Signed-off-by: Nabige Aala <[email protected]> --- drivers/phy/qualcomm/phy-qcom-edp.c | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 4d1b2c81d956..361f4e467351 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -1800,6 +1800,53 @@ static int qcom_edp_com_configure_pll_nord(const struct qcom_edp *edp) } +/* + * nord LDO configuration. + * From HPG Table 2-1-d: LDO Configuration section. + * eDP mode: 0xD1 for rates <= 8.1 Gbps, 0x00 for UHBR (>8.1 Gbps). + * DP mode: always 0x00. + * Also programs EDP2_DP_PHY_LDO_CFG: 0x03 for eDP rates <= 8.1G, 0x00 otherwise. + */ +static int qcom_edp_ldo_config_nord(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; + u32 ldo_config; + u32 phy_ldo_cfg; + + ldo_config = 0xd0; + phy_ldo_cfg = 0x03; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + writel(phy_ldo_cfg, edp->edp + DP_PHY_LDO_CFG); + + return 0; +} + +static int qcom_edp_phy_tx_lane_cfg_nord(const struct qcom_edp *edp) +{ + writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL_NORD); + writel(0x12, edp->edp + DP_PHY_TX_LN0_DRV_LVL_NORD); + writel(0x12, edp->edp + DP_PHY_TX_LN1_DRV_LVL_NORD); + writel(0x05, edp->tx0 + TXn_TX_BAND_NORD); + writel(0x05, edp->tx1 + TXn_TX_BAND_NORD); + + return 0; +} + +static int qcom_edp_phy_tx_res_cfg_nord(const struct qcom_edp *edp) +{ + writel(0x06, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); + writel(0x06, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); + writel(0x06, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); + writel(0x06, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); + writel(0x06, edp->tx0 + TXn_TX_EMP_POST1_LVL); + writel(0x06, edp->tx1 + TXn_TX_EMP_POST1_LVL); + + return 0; +} + + static const struct of_device_id qcom_edp_phy_match_table[] = { { .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, }, { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, }, -- 2.34.1
