On Fri, Sep 11, 2026 at 09:06:45PM +0530, Nabige Aala wrote:
> From: Ritesh Kumar <[email protected]>
>
> Nord uses a 38.4 MHz CXO reference with a different QSERDES v8 COM
> register layout and PLL coefficients. Add
> qcom_edp_com_configure_pll_nord() which programs all QSERDES COM PLL
> registers with link-rate-dependent values for RBR, HBR, HBR2 and
> HBR3, per HPG Table 2-1-d.
>
> Signed-off-by: Ritesh Kumar <[email protected]>
> Signed-off-by: Nabige Aala <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-edp.c | 112
> ++++++++++++++++++++++++++++++++++++
> 1 file changed, 112 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c
> b/drivers/phy/qualcomm/phy-qcom-edp.c
> index a0f4b12e561e..4d1b2c81d956 100644
> --- a/drivers/phy/qualcomm/phy-qcom-edp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
> @@ -1688,6 +1688,118 @@ static int qcom_edp_com_configure_ssc_nord(const
> struct qcom_edp *edp)
> }
>
>
> +/*
> + * Nord PLL configuration per HPG Table 2-1-d, CXO = 38.4 MHz.
> + * Supported link rates: 1.62 Gbps (RBR), 2.7 Gbps (HBR),
> + * 5.4 Gbps (HBR2), 8.1 Gbps (HBR3).
> + */
> +static int qcom_edp_com_configure_pll_nord(const struct qcom_edp *edp)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
> + u32 div_frac_start1_mode0;
> + u32 div_frac_start2_mode0;
> + u32 div_frac_start3_mode0;
> + u32 dec_start_mode0;
> + u32 lock_cmp1_mode0;
> + u32 lock_cmp2_mode0;
> + u32 lock_cmp_en;
> + u32 hsclk_sel;
> + u32 code1_mode0;
> + u32 code2_mode0;
> + u32 core_clk_div_mode0 = 0x14;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + hsclk_sel = 0x0c;
> + dec_start_mode0 = 0x54;
> + div_frac_start1_mode0 = 0x00;
> + div_frac_start2_mode0 = 0x00;
> + div_frac_start3_mode0 = 0x06;
> + lock_cmp1_mode0 = 0x37;
> + lock_cmp2_mode0 = 0x04;
> + lock_cmp_en = 0x04;
> + code1_mode0 = 0x8d;
> + code2_mode0 = 0x27;
No extra alignment, please.
> + break;
> +
> + case 2700:
> + hsclk_sel = 0x04;
> + dec_start_mode0 = 0x46;
> + div_frac_start1_mode0 = 0x00;
> + div_frac_start2_mode0 = 0x00;
> + div_frac_start3_mode0 = 0x05;
> + lock_cmp1_mode0 = 0x07;
> + lock_cmp2_mode0 = 0x07;
> + lock_cmp_en = 0x08;
> + code1_mode0 = 0xf6;
> + code2_mode0 = 0x20;
> + break;
> +
> + case 5400:
> + hsclk_sel = 0x01;
> + dec_start_mode0 = 0x46;
> + div_frac_start1_mode0 = 0x00;
> + div_frac_start2_mode0 = 0x00;
> + div_frac_start3_mode0 = 0x05;
> + lock_cmp1_mode0 = 0x0f;
> + lock_cmp2_mode0 = 0x0e;
> + lock_cmp_en = 0x08;
> + code1_mode0 = 0xf6;
> + code2_mode0 = 0x20;
> + break;
> +
> + case 8100:
> + hsclk_sel = 0x03;
> + dec_start_mode0 = 0x4f;
> + div_frac_start1_mode0 = 0x00;
> + div_frac_start2_mode0 = 0xa0;
> + div_frac_start3_mode0 = 0x01;
> + lock_cmp1_mode0 = 0x17;
> + lock_cmp2_mode0 = 0x15;
> + lock_cmp_en = 0x08;
> + code1_mode0 = 0x14;
> + code2_mode0 = 0x25;
> + core_clk_div_mode0 = 0x0a;
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> +
> + writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL_NORD);
> + writel(0x0b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL);
> + writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL);
> + writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1);
> + writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE);
> + writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT);
> + writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1);
> + writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO);
> + writel(lock_cmp_en, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN);
> + writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0);
> + writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0);
> + writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0);
> + writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0);
> + writel(div_frac_start1_mode0, edp->pll +
> DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0);
Always 0x00
> + writel(div_frac_start2_mode0, edp->pll +
> DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0);
> + writel(div_frac_start3_mode0, edp->pll +
> DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0);
> + writel(0x12, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1);
> + writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0);
> + writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0);
> + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP);
> + writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0);
> + writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0);
> + writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER);
> + writel(core_clk_div_mode0, edp->pll +
> DP_QSERDES_V8_COM_CORECLK_DIV_MODE0);
> + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL);
> + writel(0x1d, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
Not 0x1f?
> + writel(0x0f, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN);
No DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 /
DP_QSERDES_V8_COM_VCO_TUNE2_MODE0?
> + writel(code1_mode0, edp->pll +
> DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
> + writel(code2_mode0, edp->pll +
> DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
> +
> + return 0;
> +}
> +
> +
> static const struct of_device_id qcom_edp_phy_match_table[] = {
> { .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, },
> { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
