On Fri, Oct 02, 2026 at 10:07:12PM +0900, Joonhoe Kim wrote: > dpu_encoder_virt_atomic_disable() disables the physical encoders in > phys_encs[] order, i.e. the master first. With a split display (two > interfaces on one CTL, e.g. bonded DSI) the master's > dpu_encoder_helper_phys_cleanup() then resets the shared CTL while the > slave's timing engine is still running, and the source pipe is left > stalled half-way through the slave's next frame. > > A power collapse of the MDSS core GDSC clears the stall, so it normally > goes unnoticed. When MDSS stays powered across the disable (a full > modeset, or an active DP controller), the next enable scans out > nothing: black screen with the backlight on. > > Disable the slave before the master, as atomic_enable() enables them in > that order. The slave's cleanup still resets the CTL while the master is > running, but the last reset, from the master's cleanup, now happens with > both timing engines stopped. > > Tested on a Lenovo Legion Tab Y700 gen 5 (SM8850, bonded DSI video-mode > panel) with MDSS kept active: > > echo on > /sys/bus/platform/devices/9800000.display-subsystem/power/control > > DPMS off/on: black 10/10 before, picture 10/10 after. Full modesets were > not retested with this version. Only tested on this device. > > Suggested-by: Dmitry Baryshkov <[email protected]> > Fixes: 22cb02bc96ff ("drm/msm/disp/dpu: reset the datapath after timing > engine disable") > Assisted-by: LLM > Signed-off-by: Joonhoe Kim <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]> -- With best wishes Dmitry
