> Subject: [PATCH v7 12/20] drm/i915/alpm: Modify LFPS_CYCLE_COUNT > bitfield for xe3lpd
*Xe3p > > The LFPS_CYCLE_COUNT bitfield in PORT_ALPM_LFPS_CTL is widened from > 4 bits (27:24) to 7 bits (30:24) starting from xe3lpd. Add the wider register > mask and field macro, and program the cycle count using the appropriate > macro based on the display version. > > v2: Split in a separate patch. [Jouni] > > Cc: Jouni Högander <[email protected]> > Signed-off-by: Animesh Manna <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_alpm.c | 11 ++++++++++- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++ > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c > b/drivers/gpu/drm/i915/display/intel_alpm.c > index 1fd528cb7fe6..f3c0884989ce 100644 > --- a/drivers/gpu/drm/i915/display/intel_alpm.c > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c > @@ -747,12 +747,21 @@ void intel_alpm_port_configure(struct intel_dp > *intel_dp, > return; > > if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { > + int lfps_cycle = get_lfps_cycle_count(crtc_state); > + u32 lfps_cycle_val; > + > + if (DISPLAY_VER(display) >= 35) > + lfps_cycle_val = > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle); > + else > + lfps_cycle_val = > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle); > + > alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | > PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | > PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | > PORT_ALPM_CTL_SILENCE_PERIOD( > crtc_state- > >alpm_state.silence_period_sym_clocks); > - lfps_ctl_val = > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state) > ) | > + > + lfps_ctl_val = lfps_cycle_val | > > PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( > crtc_state- > >alpm_state.lfps_half_cycle_num_of_syms) | > > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 124aa74e1dbb..aee4f2592302 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -335,8 +335,10 @@ > #define PORT_ALPM_LFPS_CTL(port) > _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, > _PORT_ALPM_LFPS_CTL_B) > #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY > REG_BIT(31) > #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK > REG_GENMASK(27, 24) > +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD > REG_GENMASK(30, 24) > #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 > #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, > (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN) > +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK > _XE3LPD, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN) > /* > * The LFPS half cycle duration fields (including the first and last half > * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1. > -- > 2.43.0
