From: Konrad Dybcio <[email protected]> Fill out the register tables to enable IFPC on this SKU.
Signed-off-by: Konrad Dybcio <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 83 ++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 4ef2bd6e7ad2..5e1d91a73a4e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -736,6 +736,84 @@ static const struct adreno_reglist a702_hwcg[] = { {} }; +static const u32 a630_ifpc_reglist_regs[] = { + REG_A6XX_CP_CHICKEN_DBG, + REG_A6XX_CP_DBG_ECO_CNTL, + REG_A6XX_CP_PROTECT_CNTL, + REG_A6XX_CP_PROTECT(0), + REG_A6XX_CP_PROTECT(1), + REG_A6XX_CP_PROTECT(2), + REG_A6XX_CP_PROTECT(3), + REG_A6XX_CP_PROTECT(4), + REG_A6XX_CP_PROTECT(5), + REG_A6XX_CP_PROTECT(6), + REG_A6XX_CP_PROTECT(7), + REG_A6XX_CP_PROTECT(8), + REG_A6XX_CP_PROTECT(9), + REG_A6XX_CP_PROTECT(10), + REG_A6XX_CP_PROTECT(11), + REG_A6XX_CP_PROTECT(12), + REG_A6XX_CP_PROTECT(13), + REG_A6XX_CP_PROTECT(14), + REG_A6XX_CP_PROTECT(15), + REG_A6XX_CP_PROTECT(16), + REG_A6XX_CP_PROTECT(17), + REG_A6XX_CP_PROTECT(18), + REG_A6XX_CP_PROTECT(19), + REG_A6XX_CP_PROTECT(20), + REG_A6XX_CP_PROTECT(21), + REG_A6XX_CP_PROTECT(22), + REG_A6XX_CP_PROTECT(23), + REG_A6XX_CP_PROTECT(24), + REG_A6XX_CP_PROTECT(25), + REG_A6XX_CP_PROTECT(26), + REG_A6XX_CP_PROTECT(27), + REG_A6XX_CP_PROTECT(28), + REG_A6XX_CP_PROTECT(29), + REG_A6XX_CP_PROTECT(30), + REG_A6XX_CP_PROTECT(31), + REG_A6XX_CP_AHB_CNTL, +}; + +DECLARE_ADRENO_REGLIST_LIST(a630_ifpc_reglist); + +static const u32 a630_pwrup_reglist_regs[] = { + REG_A6XX_VSC_ADDR_MODE_CNTL, + REG_A6XX_GRAS_ADDR_MODE_CNTL, + REG_A6XX_RB_ADDR_MODE_CNTL, + REG_A6XX_PC_ADDR_MODE_CNTL, + REG_A6XX_HLSQ_ADDR_MODE_CNTL, + REG_A6XX_VFD_ADDR_MODE_CNTL, + REG_A6XX_VPC_ADDR_MODE_CNTL, + REG_A6XX_UCHE_ADDR_MODE_CNTL, + REG_A6XX_SP_ADDR_MODE_CNTL, + REG_A6XX_TPL1_ADDR_MODE_CNTL, + REG_A6XX_UCHE_WRITE_RANGE_MAX, + REG_A6XX_UCHE_WRITE_RANGE_MAX + 1, + REG_A6XX_UCHE_TRAP_BASE, + REG_A6XX_UCHE_TRAP_BASE + 1, + REG_A6XX_UCHE_WRITE_THRU_BASE, + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, + REG_A6XX_UCHE_GMEM_RANGE_MIN, + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, + REG_A6XX_UCHE_GMEM_RANGE_MAX, + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, + REG_A6XX_UCHE_FILTER_CNTL, + REG_A6XX_UCHE_CACHE_WAYS, + REG_A6XX_UCHE_MODE_CNTL, + REG_A6XX_RB_NC_MODE_CNTL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_PC_DBG_ECO_CNTL, + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, + REG_A6XX_UCHE_GBIF_GX_CONFIG, + REG_A6XX_UCHE_CLIENT_PF, + REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, + REG_A6XX_RBBM_PERFCTR_CNTL, +}; + +DECLARE_ADRENO_REGLIST_LIST(a630_pwrup_reglist); + static const struct adreno_info a6xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x06010000), @@ -1014,7 +1092,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_4GB_VA, + ADRENO_QUIRK_4GB_VA | + ADRENO_QUIRK_IFPC, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .funcs = &a6xx_gpu_funcs, .zapfw = "a630_zap.mdt", @@ -1023,6 +1102,8 @@ static const struct adreno_info a6xx_gpus[] = { .protect = &a630_protect, .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00180000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a630_pwrup_reglist, }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06040001), -- 2.56.0
