From: Konrad Dybcio <[email protected]> They reuse the existing tables, so just wire them up.
Signed-off-by: Konrad Dybcio <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 2d59f7735c90..257771d4eb4d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1012,7 +1012,8 @@ static const struct adreno_info a6xx_gpus[] = { [ADRENO_FW_GMU] = "a630_gmu.bin", }, .gmem = SZ_512K, - .quirks = ADRENO_QUIRK_4GB_VA, + .quirks = ADRENO_QUIRK_4GB_VA | + ADRENO_QUIRK_IFPC, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .funcs = &a6xx_gpu_funcs, .zapfw = "a615_zap.mdt", @@ -1021,6 +1022,8 @@ static const struct adreno_info a6xx_gpus[] = { .protect = &a630_protect, .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x0018000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a640_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( /* @@ -1044,7 +1047,8 @@ static const struct adreno_info a6xx_gpus[] = { .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_4GB_VA, + ADRENO_QUIRK_4GB_VA | + ADRENO_QUIRK_IFPC, .funcs = &a6xx_gpu_funcs, .zapfw = "a615_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1052,6 +1056,8 @@ static const struct adreno_info a6xx_gpus[] = { .protect = &a630_protect, .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00180000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a640_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -1071,12 +1077,15 @@ static const struct adreno_info a6xx_gpus[] = { .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_4GB_VA, + ADRENO_QUIRK_4GB_VA | + ADRENO_QUIRK_IFPC, .funcs = &a6xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { .protect = &a630_protect, .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00180000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a640_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -1102,6 +1111,8 @@ static const struct adreno_info a6xx_gpus[] = { .protect = &a630_protect, .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00018000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a640_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -1127,6 +1138,8 @@ static const struct adreno_info a6xx_gpus[] = { .protect = &a630_protect, .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00018000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a640_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -1143,7 +1156,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_4GB_VA, + ADRENO_QUIRK_4GB_VA | + ADRENO_QUIRK_IFPC, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .funcs = &a6xx_gpu_funcs, .zapfw = "a615_zap.mdt", @@ -1152,6 +1166,8 @@ static const struct adreno_info a6xx_gpus[] = { .protect = &a630_protect, .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00018000, + .ifpc_reglist = &a630_ifpc_reglist, + .pwrup_reglist = &a640_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, -- 2.56.0
