From: Konrad Dybcio <[email protected]> Fill out the register tables to enable IFPC on these SKUs.
Signed-off-by: Konrad Dybcio <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 122 +++++++++++++++++++++++++++++- 1 file changed, 118 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 89829fa8f4f4..2d59f7735c90 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -851,6 +851,108 @@ static const u32 a640_pwrup_reglist_regs[] = { DECLARE_ADRENO_REGLIST_LIST(a640_pwrup_reglist); +/* A650-family IFPC state also includes CP_PROTECT registers 32-47. */ +static const u32 a650_ifpc_reglist_regs[] = { + REG_A6XX_CP_CHICKEN_DBG, + REG_A6XX_CP_DBG_ECO_CNTL, + REG_A6XX_CP_PROTECT_CNTL, + REG_A6XX_CP_PROTECT(0), + REG_A6XX_CP_PROTECT(1), + REG_A6XX_CP_PROTECT(2), + REG_A6XX_CP_PROTECT(3), + REG_A6XX_CP_PROTECT(4), + REG_A6XX_CP_PROTECT(5), + REG_A6XX_CP_PROTECT(6), + REG_A6XX_CP_PROTECT(7), + REG_A6XX_CP_PROTECT(8), + REG_A6XX_CP_PROTECT(9), + REG_A6XX_CP_PROTECT(10), + REG_A6XX_CP_PROTECT(11), + REG_A6XX_CP_PROTECT(12), + REG_A6XX_CP_PROTECT(13), + REG_A6XX_CP_PROTECT(14), + REG_A6XX_CP_PROTECT(15), + REG_A6XX_CP_PROTECT(16), + REG_A6XX_CP_PROTECT(17), + REG_A6XX_CP_PROTECT(18), + REG_A6XX_CP_PROTECT(19), + REG_A6XX_CP_PROTECT(20), + REG_A6XX_CP_PROTECT(21), + REG_A6XX_CP_PROTECT(22), + REG_A6XX_CP_PROTECT(23), + REG_A6XX_CP_PROTECT(24), + REG_A6XX_CP_PROTECT(25), + REG_A6XX_CP_PROTECT(26), + REG_A6XX_CP_PROTECT(27), + REG_A6XX_CP_PROTECT(28), + REG_A6XX_CP_PROTECT(29), + REG_A6XX_CP_PROTECT(30), + REG_A6XX_CP_PROTECT(31), + REG_A6XX_CP_AHB_CNTL, + REG_A6XX_CP_PROTECT(32), + REG_A6XX_CP_PROTECT(33), + REG_A6XX_CP_PROTECT(34), + REG_A6XX_CP_PROTECT(35), + REG_A6XX_CP_PROTECT(36), + REG_A6XX_CP_PROTECT(37), + REG_A6XX_CP_PROTECT(38), + REG_A6XX_CP_PROTECT(39), + REG_A6XX_CP_PROTECT(40), + REG_A6XX_CP_PROTECT(41), + REG_A6XX_CP_PROTECT(42), + REG_A6XX_CP_PROTECT(43), + REG_A6XX_CP_PROTECT(44), + REG_A6XX_CP_PROTECT(45), + REG_A6XX_CP_PROTECT(46), + REG_A6XX_CP_PROTECT(47), +}; + +DECLARE_ADRENO_REGLIST_LIST(a650_ifpc_reglist); + +/* A650-family restore state adds bicubic weights and UCHE_CMDQ_CONFIG. */ +static const u32 a650_pwrup_reglist_regs[] = { + REG_A6XX_VSC_ADDR_MODE_CNTL, + REG_A6XX_GRAS_ADDR_MODE_CNTL, + REG_A6XX_RB_ADDR_MODE_CNTL, + REG_A6XX_PC_ADDR_MODE_CNTL, + REG_A6XX_HLSQ_ADDR_MODE_CNTL, + REG_A6XX_VFD_ADDR_MODE_CNTL, + REG_A6XX_VPC_ADDR_MODE_CNTL, + REG_A6XX_UCHE_ADDR_MODE_CNTL, + REG_A6XX_SP_ADDR_MODE_CNTL, + REG_A6XX_TPL1_ADDR_MODE_CNTL, + REG_A6XX_UCHE_WRITE_RANGE_MAX, + REG_A6XX_UCHE_WRITE_RANGE_MAX + 1, + REG_A6XX_UCHE_TRAP_BASE, + REG_A6XX_UCHE_TRAP_BASE + 1, + REG_A6XX_UCHE_WRITE_THRU_BASE, + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, + REG_A6XX_UCHE_GMEM_RANGE_MIN, + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, + REG_A6XX_UCHE_GMEM_RANGE_MAX, + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, + REG_A6XX_UCHE_FILTER_CNTL, + REG_A6XX_UCHE_CACHE_WAYS, + REG_A6XX_UCHE_MODE_CNTL, + REG_A6XX_RB_NC_MODE_CNTL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_PC_DBG_ECO_CNTL, + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, + REG_A6XX_UCHE_GBIF_GX_CONFIG, + REG_A6XX_UCHE_CLIENT_PF, + REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, + REG_A6XX_RBBM_PERFCTR_CNTL, + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A6XX_UCHE_CMDQ_CONFIG, +}; + +DECLARE_ADRENO_REGLIST_LIST(a650_pwrup_reglist); + static const struct adreno_info a6xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x06010000), @@ -1068,7 +1170,8 @@ static const struct adreno_info a6xx_gpus[] = { .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_IFPC, .funcs = &a6xx_gpu_funcs, .zapfw = "a620_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1077,6 +1180,8 @@ static const struct adreno_info a6xx_gpus[] = { .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020200, .prim_fifo_threshold = 0x00010000, + .ifpc_reglist = &a650_ifpc_reglist, + .pwrup_reglist = &a650_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -1180,7 +1285,8 @@ static const struct adreno_info a6xx_gpus[] = { .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_IFPC, .funcs = &a6xx_gpu_funcs, .zapfw = "a650_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1189,6 +1295,8 @@ static const struct adreno_info a6xx_gpus[] = { .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00300200, + .ifpc_reglist = &a650_ifpc_reglist, + .pwrup_reglist = &a650_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -1207,7 +1315,8 @@ static const struct adreno_info a6xx_gpus[] = { .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_IFPC, .funcs = &a6xx_gpu_funcs, .zapfw = "a660_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1216,6 +1325,8 @@ static const struct adreno_info a6xx_gpus[] = { .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020000, .prim_fifo_threshold = 0x00300200, + .ifpc_reglist = &a650_ifpc_reglist, + .pwrup_reglist = &a650_pwrup_reglist, }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06060300), @@ -1227,7 +1338,8 @@ static const struct adreno_info a6xx_gpus[] = { .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_IFPC, .funcs = &a6xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { .hwcg = a690_hwcg, @@ -1235,6 +1347,8 @@ static const struct adreno_info a6xx_gpus[] = { .gbif_cx = a640_gbif, .gmu_cgc_mode = 0x00020200, .prim_fifo_threshold = 0x00300200, + .ifpc_reglist = &a650_ifpc_reglist, + .pwrup_reglist = &a650_pwrup_reglist, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, -- 2.56.0
