> From: Nicholas Leippe <[EMAIL PROTECTED]>
> On Thursday 05 April 2001 03:08 am, Mike Lincoln wrote:
> > Could it be some buffer is some times allocated (word/page/whatever)
> > aligned and sometimes not?? Tends to make a big difference on Intel..
> Well, I thought about this. But looking at the source (it's pretty
> straight forward) there doesn't seem to be a way for this to happen
> since it's only a single thread. Maybe if there's some kind of
> race condition that could alter the sequence of malloc calls, but
> otherwise everything will be allocated in exactly the same order.
> Of course, this is just if the alignment change would be in the
> user space side.
>
> Even if it's not ordering allocations the same in kernel memory,
> I would think that the drm code would always attempt to allocate
> aligned blocks.
>
> Nick
The variation would be in terms of cache usage, e.g. sometimes you
get buffers that don't collide at all in the cache, other times two
or more pages happen to collide in the cache and therefore they are
competing for the same cache lines (leading to more TLB misses, page
faults and so on).
I've noticed similar behaviour, although it is affected by system load
or dragging the window around a lot (although that has surprisingly
little effect on the speed).
--
/* Bill Crawford, Unix Systems Developer, Ebone (formerly GTS Netcom) */
#include <stddiscl>
const char *addresses[] = {
"[EMAIL PROTECTED]", "[EMAIL PROTECTED]", // work
"[EMAIL PROTECTED]", "[EMAIL PROTECTED]" // home
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