Re: [Dri-devel] weird behavior?

[Gareth Hughes]

Gareth Hughes wrote:
> 
> In general, this is true.  However:
> 
> 1) All buffers (malloc()'d and DMA) are nicely aligned to at least a
> cacheline boundary.
> 
> 2) DMA buffers reside in uncached AGP memory.  Hence, caching plays no
> part in the timing of the app.

Time for a coffee.  Please ignore the last sentence, I don't know what
I'm talking about...

-- Gareth

_______________________________________________
Dri-devel mailing list
[EMAIL PROTECTED]
http://lists.sourceforge.net/lists/listinfo/dri-devel