Re: [Dri-devel] weird behavior?

[Gareth Hughes]

Bill Crawford wrote:
> 
>  The variation would be in terms of cache usage, e.g. sometimes you
> get buffers that don't collide at all in the cache, other times two
> or more pages happen to collide in the cache and therefore they are
> competing for the same cache lines (leading to more TLB misses, page
> faults and so on).

In general, this is true.  However:

1) All buffers (malloc()'d and DMA) are nicely aligned to at least a
cacheline boundary.

2) DMA buffers reside in uncached AGP memory.  Hence, caching plays no
part in the timing of the app.

-- Gareth

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