>>> The DMA test should work however, so if you update from cvs and this is working, >that's >>> a good start.
>>If it works, you should see all zeros for the registers >>before the transfer and 0x11111111, 0x22222222, etc. after the transfer. >> I suppose this is what you are talking about: Apr 27 17:43:54 tsathoggua kernel: [drm] Initialized mach64 1.0.0 20020417 on minor 0 Apr 27 17:43:54 tsathoggua kernel: [drm] Creating pool ... Apr 27 17:43:54 tsathoggua kernel: [drm] Allocating table memory ... Apr 27 17:43:54 tsathoggua kernel: [drm] Allocating data memory ... Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_S = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_T = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_W = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_SPEC_ARGB = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_Z = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_ARGB = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] (Before DMA Transfer) VERTEX_1_X_Y = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] Preparing table ... Apr 27 17:43:54 tsathoggua kernel: [drm] table[0] = 0x48fe7f00 Apr 27 17:43:54 tsathoggua kernel: [drm] table[1] = 0x00405f0f Apr 27 17:43:54 tsathoggua kernel: [drm] table[2] = 0x280000c0 Apr 27 17:43:54 tsathoggua kernel: [drm] table[3] = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] data[0] = 0x90010600 Apr 27 17:43:54 tsathoggua kernel: [drm] data[1] = 0x11111111 Apr 27 17:43:54 tsathoggua kernel: [drm] data[2] = 0x22222222 Apr 27 17:43:54 tsathoggua kernel: [drm] data[3] = 0x33333333 Apr 27 17:43:54 tsathoggua kernel: [drm] data[4] = 0x44444444 Apr 27 17:43:54 tsathoggua kernel: [drm] data[5] = 0x55555555 Apr 27 17:43:54 tsathoggua kernel: [drm] data[6] = 0x66666666 Apr 27 17:43:54 tsathoggua kernel: [drm] data[7] = 0x77777777 Apr 27 17:43:54 tsathoggua kernel: [drm] data[8] = 0x6d000000 Apr 27 17:43:54 tsathoggua kernel: [drm] data[9] = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] waiting for idle... Apr 27 17:43:54 tsathoggua kernel: [drm] BUS_CNTL = 0x7b3fa010 Apr 27 17:43:54 tsathoggua kernel: [drm] SRC_CNTL = 0x00000000 Apr 27 17:43:54 tsathoggua kernel: [drm] Apr 27 17:43:54 tsathoggua kernel: [drm] data = 0x0f5f4000 Apr 27 17:43:54 tsathoggua kernel: [drm] table = 0x0f5e8000 Apr 27 17:43:54 tsathoggua kernel: [drm] starting DMA transfer... Apr 27 17:43:54 tsathoggua kernel: [drm] starting DMA transfer... done. Apr 27 17:43:54 tsathoggua kernel: [drm] waiting for idle... Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_S = 0x11111111 Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_T = 0x22222222 Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_W = 0x33333333 Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_SPEC_ARGB = 0x00444444 Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_Z = 0x55550000 Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_ARGB = 0x66666666 Apr 27 17:43:54 tsathoggua kernel: [drm] (After DMA Transfer) VERTEX_1_X_Y = 0x77777777 Apr 27 17:43:54 tsathoggua kernel: [drm] freeing memory. Apr 27 17:43:54 tsathoggua kernel: [drm] returning ... Apr 27 17:43:54 tsathoggua kernel: [drm] Creating pci pool Apr 27 17:43:54 tsathoggua kernel: [drm] Allocating descriptor table memory Apr 27 17:43:54 tsathoggua kernel: [drm] descriptor table: cpu address: 0xcf5e8000, phys address: 0x0f5e8000 I guess it works :-) . Peter _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
