Michel Dänzer wrote:
Let me say this first: THIS PATCH DOES NOT WORK.Hi Ian,On Mit, 2003-01-22 at 00:33, Ian Romanick wrote:When I've had spare cycles, I've been working on ARB_texture_cube_map for the r100. It's almost working, but I think there something subtle the I'm missing. :(
Do you have a patch for me to try? I'd like to give tenebrae Quake a spin, which refuses to work without this extension.
I am releasing this patch to the communit in the hopes that someone else can get it to work. I'm not going to be able to spend much, if any, time working on ARB_texture_cube_map in the next few months. I've had a few requests from people that would like to get it working. This is what I've done thus far. Enjoy. :)
I suspect that there is something simple, but non-obvious that I'm missing. It would probably only take someone with hardware docs (which I don't have) a day or two to get this working.
The changes to the r200 driver (and some of the changes to the r100 driver) are just to make it easier to diff the two. I found that very helpful in even getting thing this far.
Index: lib/GL/mesa/src/drv/r200/r200_tex.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/r200/r200_tex.c,v
retrieving revision 1.3.2.6
diff -u -d -r1.3.2.6 r200_tex.c
--- lib/GL/mesa/src/drv/r200/r200_tex.c 6 Feb 2003 04:44:54 -0000 1.3.2.6
+++ lib/GL/mesa/src/drv/r200/r200_tex.c 12 Feb 2003 21:26:03 -0000
@@ -66,7 +66,7 @@
* \param twrap Wrap mode for the \a t texture coordinate
*/
-static void r200SetTexWrap( r200TexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap
)
+static void setTexWrap( r200TexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap )
{
t->pp_txfilter &= ~(R200_CLAMP_S_MASK | R200_CLAMP_T_MASK);
@@ -119,7 +119,7 @@
t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_LAST;
break;
default:
- _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
+ _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
}
t->pp_txformat_x &= ~R200_CLAMP_Q_MASK;
@@ -151,7 +151,7 @@
}
}
-static void r200SetTexMaxAnisotropy( r200TexObjPtr t, GLfloat max )
+static void setTexMaxAnisotropy( r200TexObjPtr t, GLfloat max )
{
t->pp_txfilter &= ~R200_MAX_ANISO_MASK;
@@ -176,7 +176,7 @@
* \param magf Texture magnification mode
*/
-static void r200SetTexFilter( r200TexObjPtr t, GLenum minf, GLenum magf )
+static void setTexFilter( r200TexObjPtr t, GLenum minf, GLenum magf )
{
GLuint anisotropy = (t->pp_txfilter & R200_MAX_ANISO_MASK);
@@ -238,7 +238,7 @@
}
}
-static void r200SetTexBorderColor( r200TexObjPtr t, GLubyte c[4] )
+static void setTexBorderColor( r200TexObjPtr t, GLubyte c[4] )
{
t->pp_border_color = r200PackColor( 4, c[0], c[1], c[2], c[3] );
}
@@ -250,7 +250,7 @@
* texture after it was swapped out or teximaged again.
*/
-static r200TexObjPtr r200AllocTexObj( struct gl_texture_object *texObj )
+static r200TexObjPtr allocTexObj( struct gl_texture_object *texObj )
{
r200TexObjPtr t;
@@ -267,10 +267,10 @@
make_empty_list( & t->base );
- r200SetTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR );
- r200SetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- r200SetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
- r200SetTexBorderColor( t, texObj->_BorderChan );
+ setTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR );
+ setTexMaxAnisotropy( t, texObj->MaxAnisotropy );
+ setTexFilter( t, texObj->MinFilter, texObj->MagFilter );
+ setTexBorderColor( t, texObj->_BorderChan );
}
return t;
@@ -504,14 +504,14 @@
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) r200AllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D");
return;
}
}
- /* Note, this will call r200ChooseTextureFormat */
+ /* Note, this will call ChooseTextureFormat */
_mesa_store_teximage1d(ctx, target, level, internalFormat,
width, border, format, type, pixels,
&ctx->Unpack, texObj, texImage);
@@ -536,7 +536,7 @@
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) r200AllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage1D");
return;
@@ -581,7 +581,7 @@
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) r200AllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D");
return;
@@ -606,7 +606,7 @@
* via another copy to agp memory and then a blit... Could
* eliminate one copy by going straight to (permanent) agp.
*
- * Note, this will call r200ChooseTextureFormat.
+ * Note, this will call ChooseTextureFormat.
*/
_mesa_store_teximage2d(ctx, target, level, internalFormat,
width, height, border, format, type, pixels,
@@ -650,7 +650,7 @@
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) r200AllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage2D");
return;
@@ -681,7 +681,7 @@
driSwapOutTextureObject( t );
}
else {
- t = r200AllocTexObj( texObj );
+ t = allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage3D");
return;
@@ -709,7 +709,7 @@
* via another copy to agp memory and then a blit... Could
* eliminate one copy by going straight to (permanent) agp.
*
- * Note, this will call r200ChooseTextureFormat.
+ * Note, this will call ChooseTextureFormat.
*/
_mesa_store_teximage3d(ctx, target, level, internalFormat,
width, height, depth, border,
@@ -742,7 +742,7 @@
driSwapOutTextureObject( t );
}
else {
- t = r200AllocTexObj(texObj);
+ t = allocTexObj(texObj);
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage3D");
return;
@@ -841,18 +841,18 @@
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r200SetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- r200SetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
+ setTexMaxAnisotropy( t, texObj->MaxAnisotropy );
+ setTexFilter( t, texObj->MinFilter, texObj->MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
case GL_TEXTURE_WRAP_R:
- r200SetTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR );
+ setTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR );
break;
case GL_TEXTURE_BORDER_COLOR:
- r200SetTexBorderColor( t, texObj->_BorderChan );
+ setTexBorderColor( t, texObj->_BorderChan );
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -886,9 +886,10 @@
ctx->Texture.CurrentUnit );
}
- if ( target == GL_TEXTURE_2D || target == GL_TEXTURE_1D ) {
+ if ( target == GL_TEXTURE_2D || target == GL_TEXTURE_1D ||
+ target == GL_TEXTURE_CUBE_MAP ) {
if ( texObj->DriverData == NULL ) {
- r200AllocTexObj( texObj );
+ allocTexObj( texObj );
}
}
}
@@ -975,5 +976,6 @@
driInitTextureObjects( ctx, & rmesa->swapped,
DRI_TEXMGR_DO_TEXTURE_1D
- | DRI_TEXMGR_DO_TEXTURE_2D );
+ | DRI_TEXMGR_DO_TEXTURE_2D
+ | DRI_TEXMGR_DO_TEXTURE_CUBE );
}
Index: lib/GL/mesa/src/drv/r200/r200_texmem.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/r200/r200_texmem.c,v
retrieving revision 1.3.2.5
diff -u -d -r1.3.2.5 r200_texmem.c
--- lib/GL/mesa/src/drv/r200/r200_texmem.c 6 Feb 2003 04:44:54 -0000 1.3.2.5
+++ lib/GL/mesa/src/drv/r200/r200_texmem.c 12 Feb 2003 21:26:07 -0000
@@ -282,7 +282,6 @@
{
struct gl_texture_image *texImage = NULL;
const struct gl_texture_format *texFormat;
- GLint texelsPerDword = 0;
GLuint format, pitch, offset;
GLint imageWidth, imageHeight;
GLint ret;
@@ -291,8 +290,8 @@
int level = hwlevel + t->firstLevel;
if ( R200_DEBUG & DEBUG_TEXTURE ) {
- fprintf( stderr, "%s( %p, %p ) level/width/height = %d/%d/%d\n",
- __FUNCTION__, t, t->base.tObj, level, width, height );
+ fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
+ __FUNCTION__, t, t->base.tObj, level, width, height, face );
}
ASSERT(face < 6);
@@ -358,18 +357,6 @@
texFormat = texImage->TexFormat;
-
- switch ( texFormat->TexelBytes ) {
- case 1:
- texelsPerDword = 4;
- break;
- case 2:
- texelsPerDword = 2;
- break;
- case 4:
- texelsPerDword = 1;
- break;
- }
format = t->pp_txformat & R200_TXFORMAT_FORMAT_MASK;
Index: lib/GL/mesa/src/drv/r200/r200_texstate.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/r200/r200_texstate.c,v
retrieving revision 1.4.2.7
diff -u -d -r1.4.2.7 r200_texstate.c
--- lib/GL/mesa/src/drv/r200/r200_texstate.c 7 Feb 2003 20:07:24 -0000 1.4.2.7
+++ lib/GL/mesa/src/drv/r200/r200_texstate.c 12 Feb 2003 21:26:10 -0000
@@ -236,7 +236,6 @@
assert(t->image[0][i].x == 0
|| (size < BLIT_WIDTH_BYTES && t->image[0][i].height == 1));
#endif
- curOffset += size;
if (0)
fprintf(stderr,
@@ -244,6 +243,9 @@
i, texImage->Width, texImage->Height,
t->image[0][i].x, t->image[0][i].y,
t->image[0][i].width, t->image[0][i].height, size, curOffset);
+
+ curOffset += size;
+
}
/* Align the total size of texture memory block.
Index: lib/GL/mesa/src/drv/radeon/radeon_context.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v
retrieving revision 1.20.2.10
diff -u -d -r1.20.2.10 radeon_context.c
--- lib/GL/mesa/src/drv/radeon/radeon_context.c 6 Feb 2003 18:33:06 -0000
1.20.2.10
+++ lib/GL/mesa/src/drv/radeon/radeon_context.c 12 Feb 2003 21:26:13 -0000
@@ -66,6 +66,7 @@
#define DRIVER_DATE "20021125"
+#include "vblank.h"
#include "utils.h"
#ifndef RADEON_DEBUG
int RADEON_DEBUG = (0);
@@ -307,7 +308,7 @@
4,
11, /* max 2D texture size is 2048x2048 */
0, /* 3D textures unsupported. */
- 0, /* cube textures unsupported. */
+ 11, /* max cube texture size is 2048x2048 */
0, /* texture rectangles unsupported. */
12,
GL_FALSE );
@@ -370,6 +371,9 @@
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
+ if (rmesa->radeonScreen->drmSupportsCubeMaps)
+ _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
+
radeonInitDriverFuncs( ctx );
radeonInitIoctlFuncs( ctx );
radeonInitStateFuncs( ctx );
Index: lib/GL/mesa/src/drv/radeon/radeon_context.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v
retrieving revision 1.16.2.4
diff -u -d -r1.16.2.4 radeon_context.h
--- lib/GL/mesa/src/drv/radeon/radeon_context.h 5 Dec 2002 15:26:35 -0000
1.16.2.4
+++ lib/GL/mesa/src/drv/radeon/radeon_context.h 12 Feb 2003 21:26:17 -0000
@@ -146,7 +146,6 @@
GLuint pp_txfilter; /* hardware register values */
GLuint pp_txformat;
- GLuint pp_txformat_x;
GLuint pp_txoffset; /* Image location in texmem.
All cube faces follow. */
GLuint pp_txsize; /* npot only */
@@ -251,6 +250,16 @@
#define TEX_PP_BORDER_COLOR 8
#define TEX_STATE_SIZE 9
+#define CUBE_CMD_0 0 /* 1 register follows */
+#define CUBE_PP_CUBIC_FACES 1 /* 0x1d2f */
+#define CUBE_CMD_1 2 /* 5 registers follow */
+#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x1dd0 */
+#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x1dd4 */
+#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x1dd8 */
+#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x1ddc */
+#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x1de0 */
+#define CUBE_STATE_SIZE 8
+
#define ZBS_CMD_0 0
#define ZBS_SE_ZBIAS_FACTOR 1
#define ZBS_SE_ZBIAS_CONSTANT 2
@@ -405,6 +414,7 @@
struct radeon_state_atom tcl;
struct radeon_state_atom msc;
struct radeon_state_atom tex[2];
+ struct radeon_state_atom cube[2];
struct radeon_state_atom zbs;
struct radeon_state_atom mtl;
struct radeon_state_atom mat[5];
Index: lib/GL/mesa/src/drv/radeon/radeon_screen.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v
retrieving revision 1.10.2.5
diff -u -d -r1.10.2.5 radeon_screen.c
--- lib/GL/mesa/src/drv/radeon/radeon_screen.c 26 Jan 2003 07:43:47 -0000
1.10.2.5
+++ lib/GL/mesa/src/drv/radeon/radeon_screen.c 12 Feb 2003 21:26:21 -0000
@@ -121,6 +121,9 @@
fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_IRQ_NR): %d\n", ret);
return NULL;
}
+
+ /* Check if kernel module is new enough to support cube maps */
+ screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 9);
}
}
Index: lib/GL/mesa/src/drv/radeon/radeon_screen.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h,v
retrieving revision 1.9.2.3
diff -u -d -r1.9.2.3 radeon_screen.h
--- lib/GL/mesa/src/drv/radeon/radeon_screen.h 5 Dec 2002 15:26:40 -0000 1.9.2.3
+++ lib/GL/mesa/src/drv/radeon/radeon_screen.h 12 Feb 2003 21:26:23 -0000
@@ -92,6 +92,8 @@
__DRIscreenPrivate *driScreen;
unsigned int sarea_priv_offset;
unsigned int agp_buffer_offset; /* offset in card memory space */
+
+ GLboolean drmSupportsCubeMaps; /* need radeon kernel module >= 1.9 */
} radeonScreenRec, *radeonScreenPtr;
extern radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv );
Index: lib/GL/mesa/src/drv/radeon/radeon_state_init.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v
retrieving revision 1.5.2.2
diff -u -d -r1.5.2.2 radeon_state_init.c
--- lib/GL/mesa/src/drv/radeon/radeon_state_init.c 5 Dec 2002 15:26:41 -0000
1.5.2.2
+++ lib/GL/mesa/src/drv/radeon/radeon_state_init.c 12 Feb 2003 21:26:26 -0000
@@ -113,6 +113,8 @@
CHECK( always, GL_TRUE )
CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
+CHECK( cube0, ctx->Texture.Unit[0]._ReallyEnabled == TEXTURE_CUBE_BIT )
+CHECK( cube1, ctx->Texture.Unit[1]._ReallyEnabled == TEXTURE_CUBE_BIT )
CHECK( fog, ctx->Fog.Enabled )
TCL_CHECK( tcl, GL_TRUE )
TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
@@ -228,6 +230,9 @@
ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
+ ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
+ ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/tex-1", 0 );
+
ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview",
1 );
@@ -265,6 +270,10 @@
rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0);
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1);
rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1);
+ rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_0);
+ rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_0);
+ rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_1);
+ rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_1);
rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
rmesa->hw.mtl.cmd[MTL_CMD_0] =
@@ -410,57 +419,44 @@
rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
- rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
- rmesa->hw.tex[0].cmd[TEX_PP_TXFORMAT] =
- (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
- RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
- RADEON_TXFORMAT_ST_ROUTE_STQ0 |
- (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
- (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
- rmesa->hw.tex[0].cmd[TEX_PP_TXOFFSET] = 0x2000;
- rmesa->hw.tex[0].cmd[TEX_PP_BORDER_COLOR] = 0;
- rmesa->hw.tex[0].cmd[TEX_PP_TXCBLEND] =
- (RADEON_COLOR_ARG_A_ZERO |
- RADEON_COLOR_ARG_B_ZERO |
- RADEON_COLOR_ARG_C_CURRENT_COLOR |
- RADEON_BLEND_CTL_ADD |
- RADEON_SCALE_1X |
- RADEON_CLAMP_TX);
- rmesa->hw.tex[0].cmd[TEX_PP_TXABLEND] =
- (RADEON_ALPHA_ARG_A_ZERO |
- RADEON_ALPHA_ARG_B_ZERO |
- RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
- RADEON_BLEND_CTL_ADD |
- RADEON_SCALE_1X |
- RADEON_CLAMP_TX);
- rmesa->hw.tex[0].cmd[TEX_PP_TFACTOR] = 0;
+ for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
+ rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
+ rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
+ (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
+ RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
+ (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
+ (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
+ (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
- rmesa->hw.tex[1].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
- rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] =
- (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
- RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
- RADEON_TXFORMAT_ST_ROUTE_STQ1 |
- (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
- (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
- rmesa->hw.tex[1].cmd[TEX_PP_TXOFFSET] = 0x8000;
- rmesa->hw.tex[1].cmd[TEX_PP_BORDER_COLOR] = 0;
- rmesa->hw.tex[1].cmd[TEX_PP_TXCBLEND] =
- (RADEON_COLOR_ARG_A_ZERO |
- RADEON_COLOR_ARG_B_ZERO |
- RADEON_COLOR_ARG_C_CURRENT_COLOR |
- RADEON_BLEND_CTL_ADD |
- RADEON_SCALE_1X |
- RADEON_CLAMP_TX);
- rmesa->hw.tex[1].cmd[TEX_PP_TXABLEND] =
- (RADEON_ALPHA_ARG_A_ZERO |
- RADEON_ALPHA_ARG_B_ZERO |
- RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
- RADEON_BLEND_CTL_ADD |
- RADEON_SCALE_1X |
- RADEON_CLAMP_TX);
- rmesa->hw.tex[1].cmd[TEX_PP_TFACTOR] = 0;
+ /* FIXME: What is this magic value? */
+ rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 0x2000 << (2 * i);
- /* Can oly add ST1 at the time of doing some multitex but can keep
+ rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
+ rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
+ (RADEON_COLOR_ARG_A_ZERO |
+ RADEON_COLOR_ARG_B_ZERO |
+ RADEON_COLOR_ARG_C_CURRENT_COLOR |
+ RADEON_BLEND_CTL_ADD |
+ RADEON_SCALE_1X |
+ RADEON_CLAMP_TX);
+ rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
+ (RADEON_ALPHA_ARG_A_ZERO |
+ RADEON_ALPHA_ARG_B_ZERO |
+ RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
+ RADEON_BLEND_CTL_ADD |
+ RADEON_SCALE_1X |
+ RADEON_CLAMP_TX);
+ rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
+
+ rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
+ rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = 0;
+ rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = 0;
+ rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = 0;
+ rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = 0;
+ rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = 0;
+ }
+
+ /* Can only add ST1 at the time of doing some multitex but can keep
* it after that. Errors if DIFFUSE is missing.
*/
rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
Index: lib/GL/mesa/src/drv/radeon/radeon_tex.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c,v
retrieving revision 1.17.2.7
diff -u -d -r1.17.2.7 radeon_tex.c
--- lib/GL/mesa/src/drv/radeon/radeon_tex.c 6 Feb 2003 04:44:55 -0000
1.17.2.7
+++ lib/GL/mesa/src/drv/radeon/radeon_tex.c 12 Feb 2003 21:26:30 -0000
@@ -1,29 +1,32 @@
/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c,v 1.6 2002/09/16 18:05:20
eich Exp $ */
/*
- * Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
+ VA Linux Systems Inc., Fremont, California.
+
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+/*
* Authors:
* Gareth Hughes <[EMAIL PROTECTED]>
* Brian Paul <[EMAIL PROTECTED]>
@@ -55,7 +58,7 @@
* \param twrap Wrap mode for the \a t texture coordinate
*/
-static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
+static void setTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
{
t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK);
@@ -81,6 +84,8 @@
case GL_MIRROR_CLAMP_TO_EDGE_ATI:
t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST;
break;
+ default:
+ _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
}
switch ( twrap ) {
@@ -105,10 +110,12 @@
case GL_MIRROR_CLAMP_TO_EDGE_ATI:
t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST;
break;
+ default:
+ _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
}
}
-static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
+static void setTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
{
t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK;
@@ -133,7 +140,7 @@
* \param magf Texture magnification mode
*/
-static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
+static void setTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
{
GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK);
@@ -189,7 +196,7 @@
}
}
-static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
+static void setTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
{
t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
}
@@ -201,7 +208,7 @@
* texture after it was swapped out or teximaged again.
*/
-static radeonTexObjPtr radeonAllocTexObj( struct gl_texture_object *texObj )
+static radeonTexObjPtr allocTexObj( struct gl_texture_object *texObj )
{
radeonTexObjPtr t;
@@ -222,10 +229,10 @@
make_empty_list( & t->base );
- radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
- radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
- radeonSetTexBorderColor( t, texObj->_BorderChan );
+ setTexWrap( t, texObj->WrapS, texObj->WrapT );
+ setTexMaxAnisotropy( t, texObj->MaxAnisotropy );
+ setTexFilter( t, texObj->MinFilter, texObj->MagFilter );
+ setTexBorderColor( t, texObj->_BorderChan );
}
return t;
@@ -347,14 +354,14 @@
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D");
return;
}
}
- /* Note, this will call radeonChooseTextureFormat */
+ /* Note, this will call ChooseTextureFormat */
_mesa_store_teximage1d(ctx, target, level, internalFormat,
width, border, format, type, pixels,
&ctx->Unpack, texObj, texImage);
@@ -379,7 +386,7 @@
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage1D");
return;
@@ -403,27 +410,43 @@
struct gl_texture_image *texImage )
{
driTextureObject * t = (driTextureObject *) texObj->DriverData;
+ GLuint face;
+ /* which cube face or ordinary 2D image */
+ switch (target) {
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
+ face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
+ ASSERT(face < 6);
+ break;
+ default:
+ face = 0;
+ }
if ( t != NULL ) {
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D");
return;
}
}
- /* Note, this will call radeonChooseTextureFormat */
+ /* Note, this will call ChooseTextureFormat */
_mesa_store_teximage2d(ctx, target, level, internalFormat,
width, height, border, format, type, pixels,
&ctx->Unpack, texObj, texImage);
- t->dirty_images[0] |= (1 << level);
+ t->dirty_images[face] |= (1 << level);
}
+
static void radeonTexSubImage2D( GLcontext *ctx, GLenum target, GLint level,
GLint xoffset, GLint yoffset,
GLsizei width, GLsizei height,
@@ -434,14 +457,30 @@
struct gl_texture_image *texImage )
{
driTextureObject * t = (driTextureObject *) texObj->DriverData;
+ GLuint face;
+
+ /* which cube face or ordinary 2D image */
+ switch (target) {
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
+ face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
+ ASSERT(face < 6);
+ break;
+ default:
+ face = 0;
+ }
assert( t ); /* this _should_ be true */
if ( t ) {
driSwapOutTextureObject( t );
}
else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
+ t = (driTextureObject *) allocTexObj( texObj );
if (!t) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage2D");
return;
@@ -452,7 +491,7 @@
height, format, type, pixels, packing, texObj,
texImage);
- t->dirty_images[0] |= (1 << level);
+ t->dirty_images[face] |= (1 << level);
}
@@ -540,17 +579,17 @@
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
+ setTexMaxAnisotropy( t, texObj->MaxAnisotropy );
+ setTexFilter( t, texObj->MinFilter, texObj->MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
- radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
+ setTexWrap( t, texObj->WrapS, texObj->WrapT );
break;
case GL_TEXTURE_BORDER_COLOR:
- radeonSetTexBorderColor( t, texObj->_BorderChan );
+ setTexBorderColor( t, texObj->_BorderChan );
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -584,9 +623,10 @@
ctx->Texture.CurrentUnit );
}
- if ( target == GL_TEXTURE_2D || target == GL_TEXTURE_1D ) {
+ if ( target == GL_TEXTURE_2D || target == GL_TEXTURE_1D ||
+ target == GL_TEXTURE_CUBE_MAP ) {
if ( texObj->DriverData == NULL ) {
- radeonAllocTexObj( texObj );
+ allocTexObj( texObj );
}
}
}
@@ -665,5 +705,6 @@
driInitTextureObjects( ctx, & rmesa->swapped,
DRI_TEXMGR_DO_TEXTURE_1D
- | DRI_TEXMGR_DO_TEXTURE_2D );
+ | DRI_TEXMGR_DO_TEXTURE_2D
+ | DRI_TEXMGR_DO_TEXTURE_CUBE );
}
Index: lib/GL/mesa/src/drv/radeon/radeon_texmem.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c,v
retrieving revision 1.11.14.7
diff -u -d -r1.11.14.7 radeon_texmem.c
--- lib/GL/mesa/src/drv/radeon/radeon_texmem.c 6 Feb 2003 04:44:55 -0000
1.11.14.7
+++ lib/GL/mesa/src/drv/radeon/radeon_texmem.c 12 Feb 2003 21:26:33 -0000
@@ -67,6 +67,8 @@
rmesa->state.texture.unit[i].texobj = NULL;
remove_from_list( &rmesa->hw.tex[i] );
make_empty_list( &rmesa->hw.tex[i] );
+ remove_from_list( &rmesa->hw.cube[i] );
+ make_empty_list( &rmesa->hw.cube[i] );
}
}
}
@@ -96,11 +98,11 @@
int level = hwlevel + t->firstLevel;
if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
- fprintf( stderr, "%s( %p, %p ) level/width/height = %d/%d/%d\n",
- __FUNCTION__, t, t->base.tObj, level, width, height );
+ fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
+ __FUNCTION__, t, t->base.tObj, level, width, height, face );
}
- ASSERT(face < 1);
+ ASSERT(face < 6);
/* Ensure we have a valid texture to upload */
if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) {
@@ -111,6 +113,21 @@
switch (face) {
case 0:
texImage = t->base.tObj->Image[level];
+ break;
+ case 1:
+ texImage = t->base.tObj->NegX[level];
+ break;
+ case 2:
+ texImage = t->base.tObj->PosY[level];
+ break;
+ case 3:
+ texImage = t->base.tObj->NegY[level];
+ break;
+ case 4:
+ texImage = t->base.tObj->PosZ[level];
+ break;
+ case 5:
+ texImage = t->base.tObj->NegZ[level];
break;
}
Index: lib/GL/mesa/src/drv/radeon/radeon_texstate.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v
retrieving revision 1.8.2.8
diff -u -d -r1.8.2.8 radeon_texstate.c
--- lib/GL/mesa/src/drv/radeon/radeon_texstate.c 6 Feb 2003 20:22:40 -0000
1.8.2.8
+++ lib/GL/mesa/src/drv/radeon/radeon_texstate.c 12 Feb 2003 21:26:36 -0000
@@ -38,10 +38,10 @@
#include "imports.h"
#include "colormac.h"
#include "context.h"
-#include "enums.h"
#include "macros.h"
#include "mmath.h"
#include "texformat.h"
+#include "enums.h"
#include "radeon_context.h"
#include "radeon_state.h"
@@ -133,6 +133,7 @@
switch (tObj->Target) {
case GL_TEXTURE_1D:
case GL_TEXTURE_2D:
+ case GL_TEXTURE_CUBE_MAP:
firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5);
firstLevel = MAX2(firstLevel, tObj->BaseLevel);
lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
@@ -214,6 +215,26 @@
*/
t->base.totalSize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
+ /* Setup remaining cube face blits, if needed */
+ if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
+ /* Round totalSize up to multiple of BLIT_WIDTH_BYTES */
+ const GLuint faceSize = (t->base.totalSize + BLIT_WIDTH_BYTES - 1)
+ & ~(BLIT_WIDTH_BYTES-1);
+ const GLuint lines = faceSize / BLIT_WIDTH_BYTES;
+ GLuint face;
+ /* reuse face 0 x/y/width/height - just adjust y */
+ for (face = 1; face < 6; face++) {
+ for (i = 0; i < numLevels; i++) {
+ t->image[face][i].x = t->image[0][i].x;
+ t->image[face][i].y = t->image[0][i].y + face * lines;
+ t->image[face][i].width = t->image[0][i].width;
+ t->image[face][i].height = t->image[0][i].height;
+ }
+ }
+ t->base.totalSize = 6 * faceSize; /* total texmem needed */
+ }
+
+
/* Hardware state:
*/
t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK;
@@ -221,10 +242,27 @@
t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
RADEON_TXFORMAT_HEIGHT_MASK |
- RADEON_TXFORMAT_CUBIC_MAP_ENABLE);
+ RADEON_TXFORMAT_CUBIC_MAP_ENABLE |
+ RADEON_TXFORMAT_F5_WIDTH_MASK |
+ RADEON_TXFORMAT_F5_HEIGHT_MASK);
t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
(log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
+ if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
+ assert(log2Width == log2Height);
+ t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) |
+ (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) |
+ (RADEON_TXFORMAT_CUBIC_MAP_ENABLE));
+ t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) |
+ (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) |
+ (log2Width << RADEON_FACE_WIDTH_2_SHIFT) |
+ (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) |
+ (log2Width << RADEON_FACE_WIDTH_3_SHIFT) |
+ (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) |
+ (log2Width << RADEON_FACE_WIDTH_4_SHIFT) |
+ (log2Height << RADEON_FACE_HEIGHT_4_SHIFT));
+ }
+
t->pp_txsize = (((tObj->Image[firstLevel]->Width - 1) << 0) |
((tObj->Image[firstLevel]->Height - 1) << 16));
@@ -1224,13 +1262,19 @@
RADEON_MIN_FILTER_MASK | \
RADEON_MAG_FILTER_MASK | \
RADEON_MAX_ANISO_MASK | \
+ RADEON_YUV_TO_RGB | \
+ RADEON_YUV_TEMPERATURE_MASK | \
RADEON_CLAMP_S_MASK | \
RADEON_CLAMP_T_MASK)
#define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
RADEON_TXFORMAT_HEIGHT_MASK | \
RADEON_TXFORMAT_FORMAT_MASK | \
- RADEON_TXFORMAT_ALPHA_IN_MAP)
+ RADEON_TXFORMAT_F5_WIDTH_MASK | \
+ RADEON_TXFORMAT_F5_HEIGHT_MASK | \
+ RADEON_TXFORMAT_ALPHA_IN_MAP | \
+ RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
+ RADEON_TXFORMAT_NON_POWER2)
static void import_tex_obj_state( radeonContextPtr rmesa,
@@ -1243,11 +1287,28 @@
cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
+#if 0
+ cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */
+ cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */
+#endif
cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset;
cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
- texobj->dirty_state &= ~(1<<unit);
-
RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tex[unit] );
+
+ if (texobj->base.tObj->Target == GL_TEXTURE_CUBE_MAP) {
+ GLuint *cube_cmd = RADEON_DB_STATE( cube[unit] );
+ GLuint bytesPerFace = texobj->base.totalSize / 6;
+ assert(texobj->base.totalSize % 6 == 0);
+ cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
+ cube_cmd[CUBE_PP_CUBIC_OFFSET_F1] = texobj->pp_txoffset + 1 * bytesPerFace;
+ cube_cmd[CUBE_PP_CUBIC_OFFSET_F2] = texobj->pp_txoffset + 2 * bytesPerFace;
+ cube_cmd[CUBE_PP_CUBIC_OFFSET_F3] = texobj->pp_txoffset + 3 * bytesPerFace;
+ cube_cmd[CUBE_PP_CUBIC_OFFSET_F4] = texobj->pp_txoffset + 4 * bytesPerFace;
+ cube_cmd[CUBE_PP_CUBIC_OFFSET_F5] = texobj->pp_txoffset + 5 * bytesPerFace;
+ RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.cube[unit] );
+ }
+
+ texobj->dirty_state &= ~(1<<unit);
}
@@ -1255,13 +1316,15 @@
static void set_texgen_matrix( radeonContextPtr rmesa,
GLuint unit,
- GLfloat *s_plane,
- GLfloat *t_plane )
+ const GLfloat *s_plane,
+ const GLfloat *t_plane,
+ const GLfloat *r_plane )
{
static const GLfloat scale_identity[4] = { 1,1,1,1 };
if (!TEST_EQ_4V( s_plane, scale_identity) ||
- !(TEST_EQ_4V( t_plane, scale_identity))) {
+ !TEST_EQ_4V( t_plane, scale_identity) ||
+ !TEST_EQ_4V( r_plane, scale_identity)) {
rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE<<unit;
rmesa->TexGenMatrix[unit].m[0] = s_plane[0];
rmesa->TexGenMatrix[unit].m[4] = s_plane[1];
@@ -1272,10 +1335,46 @@
rmesa->TexGenMatrix[unit].m[5] = t_plane[1];
rmesa->TexGenMatrix[unit].m[9] = t_plane[2];
rmesa->TexGenMatrix[unit].m[13] = t_plane[3];
+
+ /* NOTE: r_plane goes in the 4th row, not 3rd! */
+ rmesa->TexGenMatrix[unit].m[3] = r_plane[0];
+ rmesa->TexGenMatrix[unit].m[7] = r_plane[1];
+ rmesa->TexGenMatrix[unit].m[11] = r_plane[2];
+ rmesa->TexGenMatrix[unit].m[15] = r_plane[3];
+
rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
}
}
+/* Need this special matrix to get correct reflection map coords */
+static void
+set_texgen_reflection_matrix( radeonContextPtr rmesa, GLuint unit )
+{
+ static const GLfloat m[16] = {
+ -1, 0, 0, 0,
+ 0, -1, 0, 0,
+ 0, 0, 0, -1,
+ 0, 0, -1, 0 };
+ _math_matrix_loadf( &(rmesa->TexGenMatrix[unit]), m);
+ _math_matrix_analyse( &(rmesa->TexGenMatrix[unit]) );
+ rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE<<unit;
+}
+
+/* Need this special matrix to get correct normal map coords */
+static void
+set_texgen_normal_map_matrix( radeonContextPtr rmesa, GLuint unit )
+{
+ static const GLfloat m[16] = {
+ 1, 0, 0, 0,
+ 0, 1, 0, 0,
+ 0, 0, 0, 1,
+ 0, 0, 1, 0 };
+ _math_matrix_loadf( &(rmesa->TexGenMatrix[unit]), m);
+ _math_matrix_analyse( &(rmesa->TexGenMatrix[unit]) );
+ rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE<<unit;
+}
+
+
/* Ignoring the Q texcoord for now.
*
* Returns GL_FALSE if fallback required.
@@ -1292,7 +1391,7 @@
rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift);
rmesa->TexGenNeedNormals[unit] = 0;
- if ((texUnit->TexGenEnabled & (S_BIT|T_BIT)) == 0) {
+ if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT)) == 0) {
/* Disabled, no fallback:
*/
rmesa->TexGenEnabled |=
@@ -1303,42 +1402,58 @@
/* Very easy to do this, in fact would remove a fallback case
* elsewhere, but I haven't done it yet... Fallback:
*/
- fprintf(stderr, "fallback Q_BIT\n");
+ /*fprintf(stderr, "fallback Q_BIT\n");*/
return GL_FALSE;
}
- else if ((texUnit->TexGenEnabled & (S_BIT|T_BIT)) != (S_BIT|T_BIT) ||
- texUnit->GenModeS != texUnit->GenModeT) {
+ else if (texUnit->TexGenEnabled == (S_BIT|T_BIT) &&
+ texUnit->GenModeS == texUnit->GenModeT) {
+ /* OK */
+ rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
+ /* continue */
+ }
+ else if (texUnit->TexGenEnabled == (S_BIT|T_BIT|R_BIT) &&
+ texUnit->GenModeS == texUnit->GenModeT &&
+ texUnit->GenModeT == texUnit->GenModeR) {
+ /* OK */
+ rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
+ /* continue */
+ }
+ else {
/* Mixed modes, fallback:
*/
-/* fprintf(stderr, "fallback mixed texgen\n"); */
+ /* fprintf(stderr, "fallback mixed texgen\n"); */
return GL_FALSE;
}
- else
- rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
+
+ rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
switch (texUnit->GenModeS) {
case GL_OBJECT_LINEAR:
rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_OBJ << inputshift;
set_texgen_matrix( rmesa, unit,
texUnit->ObjectPlaneS,
- texUnit->ObjectPlaneT);
+ texUnit->ObjectPlaneT,
+ texUnit->ObjectPlaneR);
break;
case GL_EYE_LINEAR:
rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE << inputshift;
set_texgen_matrix( rmesa, unit,
texUnit->EyePlaneS,
- texUnit->EyePlaneT);
+ texUnit->EyePlaneT,
+ texUnit->EyePlaneR);
break;
case GL_REFLECTION_MAP_NV:
rmesa->TexGenNeedNormals[unit] = GL_TRUE;
rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_REFLECT<<inputshift;
+ set_texgen_reflection_matrix(rmesa, unit);
break;
case GL_NORMAL_MAP_NV:
rmesa->TexGenNeedNormals[unit] = GL_TRUE;
rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_NORMAL<<inputshift;
+ set_texgen_normal_map_matrix(rmesa, unit);
break;
case GL_SPHERE_MAP:
@@ -1438,12 +1553,53 @@
radeonSetTexImages( rmesa, tObj );
radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
if ( !t->base.memBlock )
- return GL_FALSE;
+ return GL_FALSE;
}
return GL_TRUE;
}
+static GLboolean enable_tex_cube( GLcontext *ctx, int unit )
+{
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
+ struct gl_texture_object *tObj = texUnit->_Current;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
+ GLuint face;
+
+ /* Need to load the 2d images associated with this unit.
+ */
+ if (t->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
+ t->pp_txformat &= ~RADEON_TXFORMAT_NON_POWER2;
+ for (face = 0; face < 6; face++)
+ t->base.dirty_images[face] = ~0;
+ }
+
+ ASSERT(tObj->Target == GL_TEXTURE_CUBE_MAP);
+
+ if ( t->base.dirty_images[0] || t->base.dirty_images[1] ||
+ t->base.dirty_images[2] || t->base.dirty_images[3] ||
+ t->base.dirty_images[4] || t->base.dirty_images[5] ) {
+ /* flush */
+ RADEON_FIREVERTICES( rmesa );
+ /* layout memory space, once for all faces */
+ radeonSetTexImages( rmesa, tObj );
+ }
+
+ /* upload (per face) */
+ for (face = 0; face < 6; face++) {
+ if (t->base.dirty_images[face]) {
+ radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, face );
+ }
+ }
+
+ if ( !t->base.memBlock ) {
+ /* texmem alloc failed, use s/w fallback */
+ return GL_FALSE;
+ }
+
+ return GL_TRUE;
+}
static GLboolean update_tex_common( GLcontext *ctx, int unit )
{
@@ -1526,6 +1682,10 @@
if ( texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT) ) {
return (enable_tex_2d( ctx, unit ) &&
+ update_tex_common( ctx, unit ));
+ }
+ else if ( texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
+ return (enable_tex_cube( ctx, unit ) &&
update_tex_common( ctx, unit ));
}
else if ( texUnit->_ReallyEnabled ) {
Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v
retrieving revision 1.7.2.2
diff -u -d -r1.7.2.2 radeon_common.h
--- programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h 5 Dec 2002 15:27:21
-0000 1.7.2.2
+++ programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h 12 Feb 2003 21:26:39
+-0000
@@ -354,7 +354,14 @@
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
-#define RADEON_MAX_STATE_PACKETS 73
+
+#define RADEON_EMIT_PP_CUBIC_FACES_0 73
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_0 74
+#define RADEON_EMIT_PP_CUBIC_FACES_1 75
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_1 76
+#define RADEON_EMIT_PP_CUBIC_FACES_2 77
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_2 78
+#define RADEON_MAX_STATE_PACKETS 79
/* Commands understood by cmd_buffer ioctl. More can be added but
Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v
retrieving revision 1.18.2.5
diff -u -d -r1.18.2.5 radeon_reg.h
--- programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 1 Feb 2003 19:57:28
-0000 1.18.2.5
+++ programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 12 Feb 2003 21:26:43
+-0000
@@ -1192,20 +1192,20 @@
#define RADEON_PP_CUBIC_FACES_2 0x1d2c
# define RADEON_FACE_WIDTH_1_SHIFT 0
# define RADEON_FACE_HEIGHT_1_SHIFT 4
-# define RADEON_FACE_WIDTH_1_MASK 0xf << 0)
-# define RADEON_FACE_HEIGHT_1_MASK 0xf << 4)
+# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
+# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
# define RADEON_FACE_WIDTH_2_SHIFT 8
-# define RADEON_FACE_HEIGHT_2_SHIFT 2
-# define RADEON_FACE_WIDTH_2_MASK 0xf << 8)
-# define RADEON_FACE_HEIGHT_2_MASK 0xf << 12)
-# define RADEON_FACE_WIDTH_3_SHIFT 6
-# define RADEON_FACE_HEIGHT_3_SHIFT 0
-# define RADEON_FACE_WIDTH_3_MASK 0xf << 16)
-# define RADEON_FACE_HEIGHT_3_MASK 0xf << 20)
-# define RADEON_FACE_WIDTH_4_SHIFT 4
-# define RADEON_FACE_HEIGHT_4_SHIFT 8
-# define RADEON_FACE_WIDTH_4_MASK 0xf << 24)
-# define RADEON_FACE_HEIGHT_4_MASK 0xf << 28)
+# define RADEON_FACE_HEIGHT_2_SHIFT 12
+# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
+# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
+# define RADEON_FACE_WIDTH_3_SHIFT 16
+# define RADEON_FACE_HEIGHT_3_SHIFT 20
+# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
+# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
+# define RADEON_FACE_WIDTH_4_SHIFT 24
+# define RADEON_FACE_HEIGHT_4_SHIFT 28
+# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
+# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
#define RADEON_PP_TXOFFSET_0 0x1c5c
#define RADEON_PP_TXOFFSET_1 0x1c74
Index: programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h
===================================================================
RCS file:
/cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h,v
retrieving revision 1.7.2.2
diff -u -d -r1.7.2.2 radeon.h
--- programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h 26 Jan 2003
07:43:49 -0000 1.7.2.2
+++ programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon.h 12 Feb 2003
+21:26:47 -0000
@@ -51,7 +51,7 @@
#define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 8
+#define DRIVER_MINOR 9
#define DRIVER_PATCHLEVEL 0
/* Interface history:
@@ -78,6 +78,10 @@
* Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
* R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
* 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
+ * 1.9 - Add support for cube map registers: RADEON_PP_CUBIC_FACES_[0..5]
+ * and RADEON_PP_CUBIC_OFFSET_T[0..2]_0.
+ * Added packets RADEON_EMIT_PP_CUBIC_FACES_[0..2] and
+ * RADEON_EMIT_PP_CUBIC_OFFSETS_[0..2]. (idr)
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
Index: programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h
===================================================================
RCS file:
/cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h,v
retrieving revision 1.6.2.3
diff -u -d -r1.6.2.3 radeon_drm.h
--- programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h 5 Feb
2003 22:58:55 -0000 1.6.2.3
+++ programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h 12 Feb
+2003 21:26:50 -0000
@@ -141,7 +141,14 @@
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
-#define RADEON_MAX_STATE_PACKETS 73
+
+#define RADEON_EMIT_PP_CUBIC_FACES_0 73
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_0 74
+#define RADEON_EMIT_PP_CUBIC_FACES_1 75
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_1 76
+#define RADEON_EMIT_PP_CUBIC_FACES_2 77
+#define RADEON_EMIT_PP_CUBIC_OFFSETS_2 78
+#define RADEON_MAX_STATE_PACKETS 79
/* Commands understood by cmd_buffer ioctl. More can be added but
Index: programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h
===================================================================
RCS file:
/cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h,v
retrieving revision 1.9.2.4
diff -u -d -r1.9.2.4 radeon_drv.h
--- programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h 5 Feb
2003 01:48:29 -0000 1.9.2.4
+++ programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h 12 Feb
+2003 21:26:54 -0000
@@ -325,6 +325,29 @@
#define RADEON_PP_TXFILTER_0 0x1c54
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
+#define RADEON_PP_CUBIC_FACES_0 0x1d24
+#define RADEON_PP_CUBIC_FACES_1 0x1d28
+#define RADEON_PP_CUBIC_FACES_2 0x1d2c
+
+#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
+#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
+#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
+#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
+#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
+#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
+#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
+#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
+#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
+#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
+#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
+#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
+#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
+#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
+#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
+
+#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
+#define RADEON_PP_TEX_SIZE_1 0x1d0c
+#define RADEON_PP_TEX_SIZE_2 0x1d14
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
# define RADEON_RB2D_DC_FLUSH (3 << 0)
Index: programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c
===================================================================
RCS file:
/cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c,v
retrieving revision 1.11.2.4
diff -u -d -r1.11.2.4 radeon_state.c
--- programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c 6 Feb
2003 21:39:08 -0000 1.11.2.4
+++ programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c 12 Feb
+2003 21:26:57 -0000
@@ -292,6 +292,13 @@
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+
+ { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" }, /* 73 */
+ { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" }, /* 74 */
+ { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+ { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+ { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+ { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
};
@@ -1562,7 +1569,8 @@
int radeon_cp_texture( DRM_IOCTL_ARGS )
{
- DRM_DEVICE;
+
+ DRM_DEVICE;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_texture_t tex;
drm_radeon_tex_image_t image;
@@ -1808,6 +1816,24 @@
sz = packet[id].len;
reg = packet[id].start;
+
+ if ( id > R200_EMIT_PP_CUBIC_OFFSETS_5 )
+ {
+ int buf[5];
+
+ DRM_COPY_FROM_USER_UNCHECKED( buf, data, sz * 4 );
+ DRM_ERROR( "got packet %s (%u)\n", packet[id].name, id );
+ if ( sz == 1 )
+ {
+ DRM_ERROR( "0x%04x: %08x\n", reg, buf[0] );
+ }
+ else
+ {
+ DRM_ERROR( "0x%04x: %08x %08x %08x %08x %08x\n",
+ reg, buf[0], buf[1], buf[2], buf[3], buf[4] );
+ }
+ }
+
if (sz * sizeof(int) > cmdbuf->bufsz)
return DRM_ERR(EINVAL);
