Disclaimer: I don't pretend to understand 100% how all this stuff works either, but I think my understanding has improved a little recently. :)
On Tue, 2005-03-15 at 20:07 -0500, Vladimir Dergachev wrote: > > On Tue, 15 Mar 2005, Vladimir Dergachev wrote: > > > My understanding was that for MMIO-only access: > > > > * Check that FIFO is not full before writing This one is obvious (for FIFO'd registers). :) > > * Check that GUI engine is idle before accessing framebuffer Technically you'd only have to make sure that the engine isn't operating on the same 'area' as the CPU I think, but waiting for idle is usually a good way to be on the safe side here. > > * Check that FIFO is empty before reading a register > > Forgot the forth one: some registers bypass the FIFO, so WaitForIdle for > them is not necessary. The FIFO doesn't apply to reads. It only applies to some register writes, basically the ones where queueing makes sense, i.e. mostly to acceleration related registers. I have yet to see a 'wait for idle' rule for register access anywhere. -- Earthling Michel DÃnzer | Debian (powerpc), X and DRI developer Libre software enthusiast | http://svcs.affero.net/rm.php?r=daenzer ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_ide95&alloc_id396&op=click -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
