Paul Durrant wrote:
> Liu, Jiang wrote:
>> On x86 platform, you also need to change another constraints
>> "apic_msix_max" in uts/i86pc/io/pcplusmp/apic_introp.c, this variable
>> will take effect in apic_alloc_msix_vectors() when you allocate
>> interrupt handlers. This limitation is x86 platform specific.
>>
>
> Ah ok. I'll try that. Actually apic_navail_vector() was the limit; it
> was returning 29. I'll alter the tweakable you mention. Thanks :-)
>
> BTW; is there any plan to make the apic code thread/core/package aware
> such that interrupts will get affinitized to different packages rather
> than just using consecutive CPU numbers (or is the CPU numbering
> scheme such that consecutive CPUs are actually on different packages)?
This has been the subject of much debate/consternation. Part of the
problem is that there doesn't seem to be just "one" answer. The reason
is that there is a trade off between sharing per-socket resources
between core, versus being able to make use of that sharing -- (keeping
caches warm, etc.)
Individual testing has found quite conflicting results across platforms
and test loads for what is the "optimum" distribution of interrupts
across CPU cores.
I'd just say that this is an area that is "evolving", as we struggle to
figure out what the best practice *should* be.
-- Garrett
>
> Paul
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