On 10/08/2010 12:34 PM, Chris Friesen wrote:
> On 10/08/2010 12:03 PM, Brandeburg, Jesse wrote:
>> To me this sounds extremely like an interrupt enable race, possibly at the
>> hardware level with your chipset that is implementing MSI-X
>>
>> One thing we can do is stop using autoclear (EIAC), which requires a
>> slight bit of code to be added to the MSI-X routines, to make sure the
>> driver writes EICR to clear the bit that was asserted.
>
> So basically we'd set the tx/rx queue bits in EIAC to zero at init time
> and then in ixgbe_clean_rxtx_many() (in my specific case) we'd call
> ixgbe_irq_disable_queues()? Is anything else needed?
Given that the interrupt is showing as present but masked, wouldn't we
want to stop using auto-mask instead? It seems like auto-clear isn't
causing problems.
I've attached a possible patch based on this premise, and I also moved
the interrupt disable code to
ixgbe_msix_clean_tx/ixgbe_msix_clean_rx/ixgbe_msix_clean_many where
there are comments which seem to indicate the proper place to do the
disabling. This also means that we only call disable once per interrupt
rather than every time napi calls the poll function.
I ignored the legacy code paths since they're not applicable to me.
Does this look reasonable, or am I missing something?
Thanks,
Chris
--
Chris Friesen
Software Developer
GENBAND
chris.frie...@genband.com
www.genband.com
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