From: Mark Rutland <mark.rutl...@arm.com>
The ARM architecture requires a DSB to complete TLB maintenance, with a
subsequent ISB being required to synchronize subsequent items in the
current instruction stream against the completed TLB maintenance.
The ArmEnableMmu function is currently missing the DSB, and hence the
TLB maintenance is not guaranteed to have completed at the point the MMU
is enabled. This may result in unpredictable behaviour.
The DSB subsequent to the write to SCTLR_EL1 is unnecessary; the ISB
alone is sufficient to complete all prior instructions and to
synchronise the new context with any subsequent instructions.
This patch adds missing DSBs to complete TLB maintenance, and removes
the unnecessary trailing DSB.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index bdede48724e6..28cf27fbd1b6 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -123,18 +123,20 @@ ASM_PFX(ArmEnableMmu):
4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
EL1_OR_EL2_OR_EL3(x1)
1: tlbi vmalle1
+ dsb nsh
isb
msr sctlr_el1, x0 // Write back
b 4f
2: tlbi alle2
+ dsb nsh
isb
msr sctlr_el2, x0 // Write back
b 4f
3: tlbi alle3
+ dsb nsh
isb
msr sctlr_el3, x0 // Write back
-4: dsb sy
- isb
+4: isb
ret
--
1.9.1
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