The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not bit 0 set. Furthermore, the name is inconsistent with the other definitions so rename it to TTBR_INNER_NON_CACHEABLE.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> --- ArmPkg/Include/Chipset/ArmV7Mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index f612154badc1..7fafc888fe94 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -23,7 +23,7 @@ #define TTBR_SHAREABLE BIT1 #define TTBR_NON_SHAREABLE 0 #define TTBR_INNER_CACHEABLE BIT0 -#define TTBR_NON_INNER_CACHEABLE BIT0 +#define TTBR_INNER_NON_CACHEABLE 0 #define TTBR_RGN_INNER_NON_CACHEABLE 0 #define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6 #define TTBR_RGN_INNER_WRITE_THROUGH BIT0 -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
