Bits 0 and 6 of the TTBRx system registers have different meanings
depending on whether a system implements the Multiprocessing
Extensions. So use separate memory attribute definitions for MP and
non-MP.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
ArmPkg/Include/Chipset/ArmV7Mmu.h | 13 +++++++++----
ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c | 6 +++---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h
b/ArmPkg/Include/Chipset/ArmV7Mmu.h
index 7fafc888fe94..549a5cd7d45a 100644
--- a/ArmPkg/Include/Chipset/ArmV7Mmu.h
+++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h
@@ -29,10 +29,15 @@
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
-#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH |
TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
-#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC |
TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
-#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE |
TTBR_RGN_INNER_NON_CACHEABLE )
-#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC |
TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
+#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH |
TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC |
TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE |
TTBR_INNER_NON_CACHEABLE )
+#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC |
TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+
+#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH |
TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
+#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC |
TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
+#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE |
TTBR_RGN_INNER_NON_CACHEABLE )
+#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC |
TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
#define TRANSLATION_TABLE_SECTION_COUNT 4096
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index a9cb06d78e19..b2cfdba90049 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -261,13 +261,13 @@ ArmConfigureMmu (
// Translate the Memory Attributes into Translation Table Register Attributes
if ((TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
(TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
- TTBRAttributes = TTBR_NON_CACHEABLE;
+ TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE :
TTBR_NON_CACHEABLE;
} else if ((TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
(TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
- TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
+ TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC :
TTBR_WRITE_BACK_ALLOC;
} else if ((TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
(TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
- TTBRAttributes = TTBR_WRITE_THROUGH;
+ TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH :
TTBR_WRITE_THROUGH;
} else {
ASSERT (0); // No support has been found for the attributes of the memory
region that the translation table belongs to.
return RETURN_UNSUPPORTED;
--
1.9.1
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