On 20/04/16 16:13, Jeremy Linton wrote:
On 04/20/2016 09:39 AM, G Gregory wrote:
On 20 April 2016 at 15:30, Sudeep Holla <[email protected]> wrote:
XPress-RICH3 PCIe driver initializes the root complex with the source
and target address for IO window. The root complex resources in SSDT
should match these settings.
This patch fixes the min/max base address for the IO window in Juno PCIe
root complex ACPI table.
[...]
I believe you also need to specify type translate to indicate that the
secondary side of the bridge is I/O. This part of the specification is
entirely unclear and disagrees with itself depending on which
version/paragraph of the specification you read. But the intent of that
bit for both DwordMemory and DwordIO seems to indicate that an io/memory
transaction is changing types when it crosses the bridge. That is true
for ARM devices which are writing a MMIO and a PCIe IO transaction is
being generated.
True, so what do you suggest ? How do we proceed on this then ?
Also, are you sure that the length and min/max range should be different?
Yes I got bitten by that and I failed to notice it :). I have fixed it
locally and tested correctly now.
--
Regards,
Sudeep
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