There is a case must be considered that gEventPending is 0, HighBitSet64 will
return -1, then the code will be wrong.
The code maybe:
while (gEventPending != 0) {
PendingTpl = (UINTN) HighBitSet64 (gEventPending);
if (NewTpl >= PendingTpl) {
break;
}
gEfiCurrentTpl = PendingTpl;
...
}
Thanks,
Star
-----Original Message-----
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Paolo
Bonzini
Sent: Wednesday, September 20, 2017 1:03 AM
To: Wu, Hao A <hao.a...@intel.com>; edk2-devel@lists.01.org
Cc: Dong, Eric <eric.d...@intel.com>; Zeng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH 3/6] MdeModulePkg/Tpl: Fix negative value left shift
On 19/09/2017 13:43, Hao Wu wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=695
>
> Within function CoreRestoreTpl(), left shift a negative value -2 is
> used
> in:
> "while (((-2 << NewTpl) & gEventPending) != 0) {"
>
> which involves undefined behavior.
>
> According to the C11 spec, Section 6.5.7:
>> 4 The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated
>> bits are filled with zeros. If E1 has an unsigned type, the value
>> of the result is E1 * 2^E2 , reduced modulo one more than the
>> maximum value representable in the result type. If E1 has a signed
>> type and nonnegative value, and E1 * 2^E2 is representable in the
>> result type, then that is the resulting value; otherwise, the
>> behavior is undefined.
>
> This commit explicitly cast '-2' with UINTN to resolve this issue.
>
> Cc: Steven Shi <steven....@intel.com>
> Cc: Star Zeng <star.z...@intel.com>
> Cc: Eric Dong <eric.d...@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Hao Wu <hao.a...@intel.com>
> ---
> MdeModulePkg/Core/Dxe/Event/Tpl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MdeModulePkg/Core/Dxe/Event/Tpl.c
> b/MdeModulePkg/Core/Dxe/Event/Tpl.c
> index 8ad0a33701..8c50f61117 100644
> --- a/MdeModulePkg/Core/Dxe/Event/Tpl.c
> +++ b/MdeModulePkg/Core/Dxe/Event/Tpl.c
> @@ -123,7 +123,7 @@ CoreRestoreTpl (
> //
> // Dispatch any pending events
> //
> - while (((-2 << NewTpl) & gEventPending) != 0) {
> + while (((((UINTN)-2) << NewTpl) & gEventPending) != 0) {
> gEfiCurrentTpl = (UINTN) HighBitSet64 (gEventPending);
> if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {
> CoreSetInterruptState (TRUE);
>
Maybe:
for (;;) {
PendingTpl = (UINTN) HighBitSet64 (gEventPending);
if (NewTpl >= PendingTpl) {
break;
}
gEfiCurrentTpl = PendingTpl;
}
This is much more readable, and HighBitSet64 should be efficient on most modern
processors.
Paolo
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