This patch ensures the 16500 UART is initialiazed in FIFO Polled Mode. For an example, please see:
http://www.ti.com/lit/ds/symlink/pc16550d.pdf 8.4.2 FIFO Polled Mode Operation With FCR0=1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART in the FIFO Polled Mode of operation. Leo Duran (1): MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
