Hi Star, Please see my replies below. Thanks, Leo
> -----Original Message----- > From: Zeng, Star [mailto:[email protected]] > Sent: Wednesday, June 06, 2018 4:07 AM > To: Duran, Leo <[email protected]>; Dong, Eric <[email protected]> > Cc: [email protected]; Zeng, Star <[email protected]> > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode > > Hi Leo, > > I am ok with the code change. > I was just curious about the motivation for the change. > 1. No real issue met, but just to follow the doc 8.4.2 ? > 2. Real issue met, then what is the issue ? [Duran, Leo] Real issue met (Please see answer to next questions). > 3. What is the default value of IER for your case ? [Duran, Leo] Don't care : the state machine in 16550 model required clearing IER to enter FIFO Polled mode. > > If the information are valuable, then they can be added into the commit > message for further easy maintenance. > > -----Original Message----- > From: Duran, Leo [mailto:[email protected]] > Sent: Wednesday, June 6, 2018 9:05 AM > To: Zeng, Star <[email protected]>; Dong, Eric <[email protected]> > Cc: [email protected] > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode > > Hi Star, > > I came across a 16550 model (simulation) which required clearing IER, and it > seems that's allowed in the 16650 spec, as noted here: > http://www.ti.com/lit/ds/symlink/pc16550d.pdf > > 8.4.2 FIFO Polled Mode Operation > With FCR0=1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART in > the > FIFO Polled Mode of operation. > > Thanks, > Leo. > > > -----Original Message----- > > From: Zeng, Star [mailto:[email protected]] > > Sent: Tuesday, June 05, 2018 7:43 PM > > To: Duran, Leo <[email protected]>; Dong, Eric <[email protected]> > > Cc: [email protected]; Zeng, Star <[email protected]> > > Subject: RE: [edk2] [PATCH] > MdeModulePkg/Library/BaseSerialPortLib16550: > > Ensure FIFO Polled Mode > > > > It will be better to have the information that may could be added into > > the commit message. > > > > 1. Did you meet real issue without this patch? > > 2. what is the default value of IER in your case? > > > > > > Thanks, > > Star > > -----Original Message----- > > From: Duran, Leo [mailto:[email protected]] > > Sent: Wednesday, June 6, 2018 5:21 AM > > To: Zeng, Star <[email protected]>; Dong, Eric <[email protected]> > > Cc: [email protected] > > Subject: RE: [edk2] [PATCH] > MdeModulePkg/Library/BaseSerialPortLib16550: > > Ensure FIFO Polled Mode > > > > Any updates on this patch? > > > > Do you require to know my "default value of IER"? > > > > Thanks, > > Leo. > > > > -----Original Message----- > > From: edk2-devel <[email protected]> On Behalf Of Duran, > > Leo > > Sent: Friday, May 25, 2018 8:38 AM > > To: Zeng, Star <[email protected]>; [email protected] > > Cc: Dong, Eric <[email protected]>; Zeng, Star <[email protected]> > > Subject: Re: [edk2] [PATCH] > MdeModulePkg/Library/BaseSerialPortLib16550: > > Ensure FIFO Polled Mode > > > > Don''t have access to test platform at this time. > > But will report IER value if I,m able to. > > > > Leo > > > > Get Outlook for iOS<https://aka.ms/o0ukef> > > ________________________________ > > From: Zeng, Star <[email protected]> > > Sent: Friday, May 25, 2018 6:13:16 AM > > To: Duran, Leo; [email protected] > > Cc: Dong, Eric; Zeng, Star > > Subject: RE: [edk2] [PATCH] > MdeModulePkg/Library/BaseSerialPortLib16550: > > Ensure FIFO Polled Mode > > > > Reviewed-by: Star Zeng <[email protected]> > > > > Just a little curious about > > 1. Did you meet real issue without this patch? > > 2. what is the default value of IER in your case? > > > > > > Thanks, > > Star > > -----Original Message----- > > From: edk2-devel [mailto:[email protected]] On Behalf Of > > Leo Duran > > Sent: Friday, May 25, 2018 3:08 AM > > To: [email protected] > > Cc: Dong, Eric <[email protected]>; Zeng, Star <[email protected]> > > Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > > Ensure FIFO Polled Mode > > > > Put the UART in FIFO Polled Mode by clearing IER after setting FCR. > > Also, add comments to show DLAB state for registers 0 and 1. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Leo Duran <[email protected]> > > Cc: Star Zeng <[email protected]> > > CC: Eric Dong <[email protected]> > > --- > > .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 > ++++++++++++-- > > -- > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > diff --git > > > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > > > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > > index 0ccac96..6532c4d 100644 > > --- > > > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > > +++ > > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550 > > +++ .c > > @@ -3,6 +3,8 @@ > > > > (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR> > > Copyright (c) 2006 - 2016, Intel Corporation. All rights > > reserved.<BR> > > + Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR> > > + > > This program and the accompanying materials > > are licensed and made available under the terms and conditions of > > the BSD License > > which accompanies this distribution. The full text of the license > > may be found at @@ -30,10 +32,11 @@ // // 16550 UART register > > offsets and bitfields // > > -#define R_UART_RXBUF 0 > > -#define R_UART_TXBUF 0 > > -#define R_UART_BAUD_LOW 0 > > -#define R_UART_BAUD_HIGH 1 > > +#define R_UART_RXBUF 0 // LCR_DLAB = 0 > > +#define R_UART_TXBUF 0 // LCR_DLAB = 0 > > +#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1 > > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1 > > +#define R_UART_IER 1 // LCR_DLAB = 0 > > #define R_UART_FCR 2 > > #define B_UART_FCR_FIFOE BIT0 > > #define B_UART_FCR_FIFO64 BIT5 > > @@ -554,6 +557,11 @@ SerialPortInitialize ( > > SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, > > (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | > > B_UART_FCR_FIFO64))); > > > > // > > + // Set FIFO Polled Mode by clearing IER after setting FCR // > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); > > + > > + // > > // Put Modem Control Register(MCR) into its reset state of 0x00. > > // > > SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); > > -- > > 2.7.4 > > > > _______________________________________________ > > edk2-devel mailing list > > [email protected] > > https://lists.01.org/mailman/listinfo/edk2-devel > > _______________________________________________ > > edk2-devel mailing list > > [email protected] > > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
