Reviewed-by: Ruiyu Ni <[email protected]> Thanks/Ray
> -----Original Message----- > From: edk2-devel <[email protected]> On Behalf Of Leo > Duran > Sent: Friday, May 25, 2018 3:08 AM > To: [email protected] > Cc: Dong, Eric <[email protected]>; Zeng, Star <[email protected]> > Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode > > Put the UART in FIFO Polled Mode by clearing IER after setting FCR. > Also, add comments to show DLAB state for registers 0 and 1. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leo Duran <[email protected]> > Cc: Star Zeng <[email protected]> > CC: Eric Dong <[email protected]> > --- > .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++++-- > -- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > index 0ccac96..6532c4d 100644 > --- > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > +++ > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > @@ -3,6 +3,8 @@ > > (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR> > Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> > + Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR> > + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the BSD > License > which accompanies this distribution. The full text of the license may be > found at > @@ -30,10 +32,11 @@ > // > // 16550 UART register offsets and bitfields > // > -#define R_UART_RXBUF 0 > -#define R_UART_TXBUF 0 > -#define R_UART_BAUD_LOW 0 > -#define R_UART_BAUD_HIGH 1 > +#define R_UART_RXBUF 0 // LCR_DLAB = 0 > +#define R_UART_TXBUF 0 // LCR_DLAB = 0 > +#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1 > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1 > +#define R_UART_IER 1 // LCR_DLAB = 0 > #define R_UART_FCR 2 > #define B_UART_FCR_FIFOE BIT0 > #define B_UART_FCR_FIFO64 BIT5 > @@ -554,6 +557,11 @@ SerialPortInitialize ( > SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, > (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | > B_UART_FCR_FIFO64))); > > // > + // Set FIFO Polled Mode by clearing IER after setting FCR > + // > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); > + > + // > // Put Modem Control Register(MCR) into its reset state of 0x00. > // > SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); > -- > 2.7.4 > > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
