Fixed initialization of register ss in CpuDxe.
Fixed clang compilation: ss is a 2-byte register.
--- CpuDxe/CpuGdt.c
+++ CpuDxe/CpuGdt.c
@@ -201,7 +201,7 @@ InitGlobalDescriptorTable (
//
// Update selector (segment) registers base on new GDT
//
- SetCodeSelector ((UINT16)CPU_CODE_SEL);
SetDataSelectors ((UINT16)CPU_DATA_SEL);
+ SetCodeSelector ((UINT16)CPU_CODE_SEL);
}
--
--- CpuDxe/X64/CpuAsm.S
+++ CpuDxe/X64/CpuAsm.S
@@ -51,7 +51,7 @@ ASM_PFX(InitializeExternalVectorTablePtr):
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SetCodeSelector)
ASM_PFX(SetCodeSelector):
- movq %ss, %rax
+ movw %ss, %ax
pushq %rax
movq %rsp, %rax
addq $8, %rax
--
--- CpuDxe/X64/CpuAsm.asm
+++ CpuDxe/X64/CpuAsm.asm
@@ -44,7 +44,7 @@ InitializeExternalVectorTablePtr ENDP
; );
;------------------------------------------------------------------------------
SetCodeSelector PROC PUBLIC
- mov rax, ss
+ mov ax, ss
push rax
mov rax, rsp
add rax, 8
--
On 01/17/2013 05:54 PM, Kirkendall, Garrett wrote:
> For the iretq versions of CpuAsm, you have to use SS. I don't see anywhere
> in the patch that you have guaranteed that SS has the correct selector for
> the GDT that was just loaded prior to the call to SetCodeSelector. Since in
> this case selector 0x0008 happens to be the same in the original and new
> GDTs, you don't see an error. But, that should probably be fixed.
>
> BTW, I vote for the iretq versions of SetCodeSelector, obviously.
>
> Thanks,
>
> Garrett Kirkendall
>
> -----Original Message-----
> From: Konstantin Filatov [mailto:kfila...@parallels.com]
> Sent: Thursday, January 17, 2013 5:17 AM
> To: edk2-devel@lists.sourceforge.net
> Subject: Re: [edk2] Make the upper memory usable.
>
> Hello,
>
> this patch for CpuDxe has been developed further, so now I send an actual
> version of it. I still think it will useful for all you.
>
> Best regards,
> Konstantin Filatov
>
> Really this is a patch set, and I didn't merge it into a large patch
> applicable to the actual edk2-source. I have a reason for it. In this way
> this patch set will easier to understand, and it will scrutinized surely
> before a commit.
>
> The beginning of this patch set.
>
> fixed SetCodeSelector
>
> --- CpuDxe/X64/CpuAsm.S
> +++ CpuDxe/X64/CpuAsm.S
> @@ -51,13 +51,13 @@ ASM_PFX(InitializeExternalVectorTablePtr):
>
> #------------------------------------------------------------------------------
> ASM_GLOBAL ASM_PFX(SetCodeSelector)
> ASM_PFX(SetCodeSelector):
> - subq $0x10, %rsp
> + subq $0x14, %rsp
> leaq L_setCodeSelectorLongJump(%rip), %rax
> movq %rax, (%rsp)
> - movw %cx, 4(%rsp)
> - .byte 0xFF, 0x2C, 0x24 # jmp (%rsp) note:fword jmp
> + movw %cx, 8(%rsp)
> + .byte 0x48, 0xFF, 0x2C, 0x24 # REX.W jmp (%rsp) note:fword jmp
> L_setCodeSelectorLongJump:
> - addq $0x10, %rsp
> + addq $0x14, %rsp
> ret
>
>
> #------------------------------------------------------------------------------
> --
>
> fixed a bug in CpuDxe in EFI
> IA32_DESCRIPTOR can have 64bit field Base regardless the name.
>
> --- CpuDxe/CpuDxe.c
> +++ CpuDxe/CpuDxe.c
> @@ -1192,7 +1192,7 @@ InitInterruptDescriptorTable (
> //
> IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
> IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
> - IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable)& (BASE_4GB-1));
> + IdtPtr->Base = (UINTN)(VOID*) gIdtTable;
> IdtPtr->Limit = (UINT16) (sizeof (gIdtTable) - 1);
>
> AsmWriteIdtr (IdtPtr);
> --
> --- CpuDxe/CpuGdt.c
> +++ CpuDxe/CpuGdt.c
> @@ -194,7 +194,7 @@ InitGlobalDescriptorTable (
> //
> // Write GDT register
> //
> - gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
> + gdtPtr.Base = (UINTN)(VOID*) gdt;
> gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
> AsmWriteGdtr (&gdtPtr);
>
>
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