Thanks Garrett for the contribution, I have reviewed the different shifts in the AArch64 MMU code after your comment.
Unfortunately, I have not been able to validate these changes but they sound relevant. What do you think about replacing your type castings with these ones less verbose (see attached patch). Olivier From: Kirkendall, Garrett [mailto:[email protected]] Sent: 11 October 2013 19:39 To: [email protected] Subject: [edk2] PATCH AARCH64: ArmPkg/Include/Chipset/AArch64Mmu.h fix translation table address calculations for AARCH64 Please see attached patch which fixes translation table address calculations for AARCH64. It adds typecasts to allow shift left to support above 32-bits for these macros. Please be aware, I did not validate/change the TT_GET_ENTRY_FOR_ADDRESS, or the TT_LAST_BLOCK_ADDRESS #defines. You might want to check and make sure those will do what you think as well. Garrett Kirkendall Description: Description: Description: purple SMTS Firmware Engineer | AMD Technology & Engineering 7171 Southwest Parkway, Austin, TX 78735 USA Description: Description: Description: image004 <https://www.facebook.com/AMD> facebook | <http://www.amd.com/> amd.com
<<image001.png>>
<<image002.png>>
TranslationTableAddressCalculation_AArch64Mmu-h-v2.patch
Description: Binary data
------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134071&iu=/4140/ostg.clktrk
_______________________________________________ edk2-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/edk2-devel
