Please see attached patch which fixes translation table address calculations for AARCH64. It adds typecasts to allow shift left to support above 32-bits for these macros.
Please be aware, I did not validate/change the TT_GET_ENTRY_FOR_ADDRESS, or the TT_LAST_BLOCK_ADDRESS #defines. You might want to check and make sure those will do what you think as well. Garrett Kirkendall [Description: Description: Description: purple] SMTS Firmware Engineer | AMD Technology & Engineering 7171 Southwest Parkway, Austin, TX 78735 USA [Description: Description: Description: image004] facebook<https://www.facebook.com/AMD> | amd.com<http://www.amd.com/>
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TranslationTableAddressCalculation_AArch64Mmu-h.patch
Description: TranslationTableAddressCalculation_AArch64Mmu-h.patch
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