That patch works for me. Garrett Kirkendall [Description: Description: Description: purple] SMTS Firmware Engineer | AMD Technology & Engineering 7171 Southwest Parkway, Austin, TX 78735 USA O +(1) 512-602-3255 [Description: Description: Description: image004] facebook<https://www.facebook.com/AMD> | amd.com<http://www.amd.com/>
From: Olivier Martin [mailto:[email protected]] Sent: Monday, October 14, 2013 11:02 AM To: [email protected] Subject: Re: [edk2] PATCH AARCH64: ArmPkg/Include/Chipset/AArch64Mmu.h fix translation table address calculations for AARCH64 Thanks Garrett for the contribution, I have reviewed the different shifts in the AArch64 MMU code after your comment. Unfortunately, I have not been able to validate these changes but they sound relevant. What do you think about replacing your type castings with these ones less verbose (see attached patch). Olivier From: Kirkendall, Garrett [mailto:[email protected]] Sent: 11 October 2013 19:39 To: [email protected]<mailto:[email protected]> Subject: [edk2] PATCH AARCH64: ArmPkg/Include/Chipset/AArch64Mmu.h fix translation table address calculations for AARCH64 Please see attached patch which fixes translation table address calculations for AARCH64. It adds typecasts to allow shift left to support above 32-bits for these macros. Please be aware, I did not validate/change the TT_GET_ENTRY_FOR_ADDRESS, or the TT_LAST_BLOCK_ADDRESS #defines. You might want to check and make sure those will do what you think as well. Garrett Kirkendall [Description: Description: Description: purple] SMTS Firmware Engineer | AMD Technology & Engineering 7171 Southwest Parkway, Austin, TX 78735 USA [Description: Description: Description: image004] facebook<https://www.facebook.com/AMD> | amd.com<http://www.amd.com/>
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